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Rename Ariane to CVA6 #9

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merged 4 commits into from
Nov 6, 2020
Merged

Rename Ariane to CVA6 #9

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27157f7
Rename Ariane to CVA6
abejgonzalez Nov 4, 2020
3f0513a
Fix submodule issues
abejgonzalez Nov 5, 2020
e357637
Bugfix sv file from scala
abejgonzalez Nov 5, 2020
8a11e2c
Fix Ariane instantiation
abejgonzalez Nov 5, 2020
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6 changes: 3 additions & 3 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
[submodule "src/main/resources/vsrc/ariane"]
path = src/main/resources/vsrc/ariane
url = https://github.com/pulp-platform/ariane.git
[submodule "src/main/resources/vsrc/cva6"]
path = src/main/resources/vsrc/cva6
url = https://github.com/openhwgroup/cva6.git
4 changes: 2 additions & 2 deletions README.md
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# Ariane Wrapper
# CVA6 Wrapper

This wraps up the Ariane 6-stage RISC-V CPU (https://github.com/pulp-platform/ariane) into a Rocket Chip based tile to be used in Chipyard.
This wraps up the CVA6 6-stage RISC-V CPU (formerly known as Ariane) (https://github.com/openhwgroup/cva6) into a Rocket Chip based tile to be used in Chipyard.

For more information on how to use this wrapper, refer to (https://github.com/ucb-bar/chipyard).
2 changes: 1 addition & 1 deletion build.sbt
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Expand Up @@ -2,7 +2,7 @@ organization := "edu.berkeley.cs"

version := "1.0"

name := "ariane"
name := "cva6"

scalaVersion := "2.12.4"

Expand Down
2 changes: 1 addition & 1 deletion ariane.mk → cva6.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -7,4 +7,4 @@
##################################################################

# requirements needed to run the generator
EXTRA_GENERATOR_REQS += $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v)
EXTRA_GENERATOR_REQS += $(call lookup_srcs,$(base_dir)/generators/cva6,sv) $(call lookup_srcs,$(base_dir)/generators/cva6,v)
2 changes: 1 addition & 1 deletion src/main/resources/vsrc/.gitignore
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
ArianeCoreBlackbox.preprocessed.sv
CVA6CoreBlackbox.preprocessed.sv
10 changes: 5 additions & 5 deletions ...main/resources/vsrc/ArianeCoreBlackbox.sv → src/main/resources/vsrc/CVA6CoreBlackbox.sv
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
// ******************************************************************
// Wrapper for the Ariane Core
// Wrapper for the CVA6 Core
// ******************************************************************

`define HARTID_LEN 64

module ArianeCoreBlackbox
module CVA6CoreBlackbox
#(
parameter TRACEPORT_SZ = 0,
parameter XLEN = 0,
Expand Down Expand Up @@ -101,7 +101,7 @@ module ArianeCoreBlackbox
input [AXI_USER_WIDTH-1:0] axi_resp_i_r_bits_user
);

localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
localparam ariane_pkg::ariane_cfg_t CVA6SocCfg = '{
RASDepth: RAS_ENTRIES,
BTBEntries: BTB_ENTRIES,
BHTEntries: BHT_ENTRIES,
Expand Down Expand Up @@ -132,7 +132,7 @@ module ArianeCoreBlackbox
traced_instr_pkg::trace_port_t tp_if;

ariane #(
.ArianeCfg ( ArianeSocCfg )
.ArianeCfg ( CVA6SocCfg )
) i_ariane (
.clk_i,
.rst_ni,
Expand All @@ -148,7 +148,7 @@ module ArianeCoreBlackbox
);
`else
ariane #(
.ArianeCfg ( ArianeSocCfg )
.ArianeCfg ( CVA6SocCfg )
) i_ariane (
.clk_i,
.rst_ni,
Expand Down
208 changes: 104 additions & 104 deletions src/main/resources/vsrc/Makefile
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Original file line number Diff line number Diff line change
@@ -1,128 +1,128 @@
#########################################################################################
# pre-process ariane into a single blackbox file
# pre-process CVA6 into a single blackbox file
#########################################################################################
base_dir=$(abspath ../../../../../..)
vsrc_dir=$(abspath .)
ariane_dir=$(vsrc_dir)/ariane
cva6_dir=$(vsrc_dir)/cva6

# name of output pre-processed verilog file
PREPROC_VERILOG = ArianeCoreBlackbox.preprocessed.sv
PREPROC_VERILOG = CVA6CoreBlackbox.preprocessed.sv

.PHONY: default $(PREPROC_VERILOG)
default: $(PREPROC_VERILOG)

#########################################################################################
# includes and vsrcs
#########################################################################################
ARIANE_PKGS = \
$(ariane_dir)/include/riscv_pkg.sv \
$(ariane_dir)/src/riscv-dbg/src/dm_pkg.sv \
$(ariane_dir)/include/ariane_pkg.sv \
$(ariane_dir)/include/std_cache_pkg.sv \
$(ariane_dir)/include/wt_cache_pkg.sv \
$(ariane_dir)/src/axi/src/axi_pkg.sv \
$(ariane_dir)/src/register_interface/src/reg_intf.sv \
$(ariane_dir)/src/register_interface/src/reg_intf_pkg.sv \
$(ariane_dir)/include/axi_intf.sv \
$(ariane_dir)/tb/ariane_soc_pkg.sv \
$(ariane_dir)/include/ariane_axi_pkg.sv \
$(ariane_dir)/src/fpu/src/fpnew_pkg.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
$(ariane_dir)/include/traced_instr_pkg.sv
CVA6_PKGS = \
$(cva6_dir)/include/riscv_pkg.sv \
$(cva6_dir)/src/riscv-dbg/src/dm_pkg.sv \
$(cva6_dir)/include/ariane_pkg.sv \
$(cva6_dir)/include/std_cache_pkg.sv \
$(cva6_dir)/include/wt_cache_pkg.sv \
$(cva6_dir)/src/axi/src/axi_pkg.sv \
$(cva6_dir)/src/register_interface/src/reg_intf.sv \
$(cva6_dir)/src/register_interface/src/reg_intf_pkg.sv \
$(cva6_dir)/include/axi_intf.sv \
$(cva6_dir)/tb/ariane_soc_pkg.sv \
$(cva6_dir)/include/ariane_axi_pkg.sv \
$(cva6_dir)/src/fpu/src/fpnew_pkg.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
$(cva6_dir)/include/traced_instr_pkg.sv

ARIANE_VSRCS = \
$(ariane_dir)/src/alu.sv \
$(ariane_dir)/src/amo_buffer.sv \
$(ariane_dir)/src/ariane_regfile_ff.sv \
$(ariane_dir)/src/ariane.sv \
$(ariane_dir)/src/axi_shim.sv \
$(ariane_dir)/src/branch_unit.sv \
$(ariane_dir)/src/commit_stage.sv \
$(ariane_dir)/src/compressed_decoder.sv \
$(ariane_dir)/src/controller.sv \
$(ariane_dir)/src/csr_buffer.sv \
$(ariane_dir)/src/csr_regfile.sv \
$(ariane_dir)/src/decoder.sv \
$(ariane_dir)/src/ex_stage.sv \
$(ariane_dir)/src/fpu_wrap.sv \
$(ariane_dir)/src/id_stage.sv \
$(ariane_dir)/src/instr_realign.sv \
$(ariane_dir)/src/issue_read_operands.sv \
$(ariane_dir)/src/issue_stage.sv \
$(ariane_dir)/src/load_store_unit.sv \
$(ariane_dir)/src/load_unit.sv \
$(ariane_dir)/src/mmu.sv \
$(ariane_dir)/src/multiplier.sv \
$(ariane_dir)/src/mult.sv \
$(ariane_dir)/src/perf_counters.sv \
$(ariane_dir)/src/ptw.sv \
$(ariane_dir)/src/re_name.sv \
$(ariane_dir)/src/scoreboard.sv \
$(ariane_dir)/src/serdiv.sv \
$(ariane_dir)/src/store_buffer.sv \
$(ariane_dir)/src/store_unit.sv \
$(ariane_dir)/src/tlb.sv \
$(ariane_dir)/src/fpu/src/fpnew_cast_multi.sv \
$(ariane_dir)/src/fpu/src/fpnew_classifier.sv \
$(ariane_dir)/src/fpu/src/fpnew_divsqrt_multi.sv \
$(ariane_dir)/src/fpu/src/fpnew_fma_multi.sv \
$(ariane_dir)/src/fpu/src/fpnew_fma.sv \
$(ariane_dir)/src/fpu/src/fpnew_noncomp.sv \
$(ariane_dir)/src/fpu/src/fpnew_opgroup_block.sv \
$(ariane_dir)/src/fpu/src/fpnew_opgroup_fmt_slice.sv \
$(ariane_dir)/src/fpu/src/fpnew_opgroup_multifmt_slice.sv \
$(ariane_dir)/src/fpu/src/fpnew_rounding.sv \
$(ariane_dir)/src/fpu/src/fpnew_top.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \
$(ariane_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
$(ariane_dir)/src/frontend/bht.sv \
$(ariane_dir)/src/frontend/btb.sv \
$(ariane_dir)/src/frontend/frontend.sv \
$(ariane_dir)/src/frontend/instr_queue.sv \
$(ariane_dir)/src/frontend/instr_scan.sv \
$(ariane_dir)/src/frontend/ras.sv \
$(ariane_dir)/src/cache_subsystem/wt_icache.sv \
$(ariane_dir)/src/cache_subsystem/wt_dcache_wbuffer.sv \
$(ariane_dir)/src/cache_subsystem/wt_dcache.sv \
$(ariane_dir)/src/cache_subsystem/wt_dcache_missunit.sv \
$(ariane_dir)/src/cache_subsystem/wt_dcache_mem.sv \
$(ariane_dir)/src/cache_subsystem/wt_dcache_ctrl.sv \
$(ariane_dir)/src/cache_subsystem/wt_cache_subsystem.sv \
$(ariane_dir)/src/cache_subsystem/wt_axi_adapter.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_res_tbl.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_riscv_amos.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_riscv_atomics.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv \
$(ariane_dir)/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv \
$(ariane_dir)/src/common_cells/src/exp_backoff.sv \
$(ariane_dir)/src/util/axi_master_connect.sv \
$(ariane_dir)/src/util/sram.sv \
$(ariane_dir)/src/fpga-support/rtl/SyncSpRamBeNx64.sv \
$(ariane_dir)/src/common_cells/src/unread.sv \
$(ariane_dir)/src/common_cells/src/stream_arbiter.sv \
$(ariane_dir)/src/common_cells/src/stream_arbiter_flushable.sv \
$(ariane_dir)/src/common_cells/src/fifo_v3.sv \
$(ariane_dir)/src/common_cells/src/lzc.sv \
$(ariane_dir)/src/common_cells/src/popcount.sv \
$(ariane_dir)/src/common_cells/src/rr_arb_tree.sv \
$(ariane_dir)/src/common_cells/src/lfsr_8bit.sv \
$(ariane_dir)/src/common_cells/src/shift_reg.sv
CVA6_VSRCS = \
$(cva6_dir)/src/alu.sv \
$(cva6_dir)/src/amo_buffer.sv \
$(cva6_dir)/src/ariane_regfile_ff.sv \
$(cva6_dir)/src/ariane.sv \
$(cva6_dir)/src/axi_shim.sv \
$(cva6_dir)/src/branch_unit.sv \
$(cva6_dir)/src/commit_stage.sv \
$(cva6_dir)/src/compressed_decoder.sv \
$(cva6_dir)/src/controller.sv \
$(cva6_dir)/src/csr_buffer.sv \
$(cva6_dir)/src/csr_regfile.sv \
$(cva6_dir)/src/decoder.sv \
$(cva6_dir)/src/ex_stage.sv \
$(cva6_dir)/src/fpu_wrap.sv \
$(cva6_dir)/src/id_stage.sv \
$(cva6_dir)/src/instr_realign.sv \
$(cva6_dir)/src/issue_read_operands.sv \
$(cva6_dir)/src/issue_stage.sv \
$(cva6_dir)/src/load_store_unit.sv \
$(cva6_dir)/src/load_unit.sv \
$(cva6_dir)/src/mmu.sv \
$(cva6_dir)/src/multiplier.sv \
$(cva6_dir)/src/mult.sv \
$(cva6_dir)/src/perf_counters.sv \
$(cva6_dir)/src/ptw.sv \
$(cva6_dir)/src/re_name.sv \
$(cva6_dir)/src/scoreboard.sv \
$(cva6_dir)/src/serdiv.sv \
$(cva6_dir)/src/store_buffer.sv \
$(cva6_dir)/src/store_unit.sv \
$(cva6_dir)/src/tlb.sv \
$(cva6_dir)/src/fpu/src/fpnew_cast_multi.sv \
$(cva6_dir)/src/fpu/src/fpnew_classifier.sv \
$(cva6_dir)/src/fpu/src/fpnew_divsqrt_multi.sv \
$(cva6_dir)/src/fpu/src/fpnew_fma_multi.sv \
$(cva6_dir)/src/fpu/src/fpnew_fma.sv \
$(cva6_dir)/src/fpu/src/fpnew_noncomp.sv \
$(cva6_dir)/src/fpu/src/fpnew_opgroup_block.sv \
$(cva6_dir)/src/fpu/src/fpnew_opgroup_fmt_slice.sv \
$(cva6_dir)/src/fpu/src/fpnew_opgroup_multifmt_slice.sv \
$(cva6_dir)/src/fpu/src/fpnew_rounding.sv \
$(cva6_dir)/src/fpu/src/fpnew_top.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \
$(cva6_dir)/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
$(cva6_dir)/src/frontend/bht.sv \
$(cva6_dir)/src/frontend/btb.sv \
$(cva6_dir)/src/frontend/frontend.sv \
$(cva6_dir)/src/frontend/instr_queue.sv \
$(cva6_dir)/src/frontend/instr_scan.sv \
$(cva6_dir)/src/frontend/ras.sv \
$(cva6_dir)/src/cache_subsystem/wt_icache.sv \
$(cva6_dir)/src/cache_subsystem/wt_dcache_wbuffer.sv \
$(cva6_dir)/src/cache_subsystem/wt_dcache.sv \
$(cva6_dir)/src/cache_subsystem/wt_dcache_missunit.sv \
$(cva6_dir)/src/cache_subsystem/wt_dcache_mem.sv \
$(cva6_dir)/src/cache_subsystem/wt_dcache_ctrl.sv \
$(cva6_dir)/src/cache_subsystem/wt_cache_subsystem.sv \
$(cva6_dir)/src/cache_subsystem/wt_axi_adapter.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_res_tbl.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_riscv_amos.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_riscv_atomics.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv \
$(cva6_dir)/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv \
$(cva6_dir)/src/common_cells/src/exp_backoff.sv \
$(cva6_dir)/src/util/axi_master_connect.sv \
$(cva6_dir)/src/util/sram.sv \
$(cva6_dir)/src/fpga-support/rtl/SyncSpRamBeNx64.sv \
$(cva6_dir)/src/common_cells/src/unread.sv \
$(cva6_dir)/src/common_cells/src/stream_arbiter.sv \
$(cva6_dir)/src/common_cells/src/stream_arbiter_flushable.sv \
$(cva6_dir)/src/common_cells/src/fifo_v3.sv \
$(cva6_dir)/src/common_cells/src/lzc.sv \
$(cva6_dir)/src/common_cells/src/popcount.sv \
$(cva6_dir)/src/common_cells/src/rr_arb_tree.sv \
$(cva6_dir)/src/common_cells/src/lfsr_8bit.sv \
$(cva6_dir)/src/common_cells/src/shift_reg.sv

ARIANE_WRAPPER = \
$(vsrc_dir)/ArianeCoreBlackbox.sv
CVA6_WRAPPER = \
$(vsrc_dir)/CVA6CoreBlackbox.sv

ALL_VSRCS = $(ARIANE_PKGS) $(ARIANE_VSRCS) $(ARIANE_WRAPPER)
ALL_VSRCS = $(CVA6_PKGS) $(CVA6_VSRCS) $(CVA6_WRAPPER)

#########################################################################################
# pre-process using verilator
#########################################################################################

lookup_dirs = $(shell find -L $(ariane_dir) -name target -prune -o -type d -print 2> /dev/null | grep '.*/\($(1)\)$$')
lookup_dirs = $(shell find -L $(cva6_dir) -name target -prune -o -type d -print 2> /dev/null | grep '.*/\($(1)\)$$')
INC_DIR_NAMES ?= include inc
INC_DIRS ?= $(foreach dir_name,$(INC_DIR_NAMES),$(call lookup_dirs,$(dir_name)))

Expand Down
0 src/main/resources/vsrc/ariane → src/main/resources/vsrc/cva6
Open in desktop
Submodule cva6 updated from 000000 to 1793be
10 changes: 5 additions & 5 deletions src/main/scala/ArianeCoreBlackbox.scala → src/main/scala/CVA6CoreBlackbox.scala
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,11 @@

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Ariane Tile Wrapper
// CVA6 Tile Wrapper
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------

package ariane
package cva6

import sys.process._

Expand All @@ -32,7 +32,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._

class ArianeCoreBlackbox(
class CVA6CoreBlackbox(
traceportEnabled: Boolean,
traceportSz: Int,
xLen: Int,
Expand Down Expand Up @@ -139,10 +139,10 @@ class ArianeCoreBlackbox(
require((cacheRegCnt <= cacheRegAvail) && (cacheRegBase.length <= cacheRegAvail) && (cacheRegSz.length <= cacheRegAvail), s"Currently only supports $cacheRegAvail cacheable regions")

// pre-process the verilog to remove "includes" and combine into one file
val make = "make -C generators/ariane/src/main/resources/vsrc default "
val make = "make -C generators/cva6/src/main/resources/vsrc default "
val proc = if (traceportEnabled) make + "EXTRA_PREPROC_DEFINES=FIRESIM_TRACE" else make
require (proc.! == 0, "Failed to run preprocessing step")

// add wrapper/blackbox after it is pre-processed
addResource("/vsrc/ArianeCoreBlackbox.preprocessed.sv")
addResource("/vsrc/CVA6CoreBlackbox.preprocessed.sv")
}
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