update tile reset control registers for TileResetDomain

[timsnyder-siv]

I'm trying to use 60d5da8 with rocket that contains chipsalliance/rocket-chip#2641 . That PR changes freechips.rocketchip.tile.TilePRCIDomain so that it no longer has a ClockSinkNode. It has a TileResetDomain that now has the ClockSinkNode.

and I'm running into:

info] Compiling 20 Scala sources to /home/centos/federation_201214/testchipip/target/scala-2.12/classes ...
[error] /home/centos/federation_201214/testchipip/src/main/scala/TileResetCtrl.scala:49:11: value clockSinkNode is not a member of freechips.rocketchip.tile.TilePRCIDomain[_$1]
[error]         d.clockSinkNode.portParams(0).name.get -> r_tile_resets(i).io.q
[error]           ^

I'm starting to look into how to address this but thought I'd file an issue in case @jerryz123, or @hcook or @davidbiancolin already have looked at this.