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bit casts update
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@kassane
kassane committed Jul 1, 2023
1 parent 2018aea commit 2f76fe7
Showing 1 changed file with 21 additions and 21 deletions.
42 changes: 21 additions & 21 deletions bindings/zig/sample/sample_riscv_zig.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ fn hook_memalloc(uc: ?*unicornC.uc_engine, @"type": unicornC.uc_mem_type, addres
_ = user_data;
_ = @"type";
var algined_address = address & 0xFFFFFFFFFFFFF000;
var aligned_size = (@intCast(u32, size / 0x1000) + 1) * 0x1000;
var aligned_size = (@as(u32, @intCast(size / 0x1000)) + 1) * 0x1000;

log.info(">>> Allocating block at 0x{} (0x{}), block size = 0x{} (0x{})", .{ address, algined_address, size, aligned_size });

Expand Down Expand Up @@ -72,30 +72,30 @@ fn test_recover_from_illegal() !void {
try unicorn.uc_mem_map(uc, ADDRESS, 2 * 1024 * 1024, unicornC.UC_PROT_ALL);

// auto-allocate memory on access
try unicorn.uc_hook_add(uc, &mem_alloc, unicornC.UC_HOOK_MEM_UNMAPPED, @ptrCast(?*anyopaque, @constCast(&hook_memalloc)), null, 1, 0);
try unicorn.uc_hook_add(uc, &mem_alloc, unicornC.UC_HOOK_MEM_UNMAPPED, @as(?*anyopaque, @ptrCast(@constCast(&hook_memalloc))), null, 1, 0);

// tracing all basic blocks with customized callback
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @ptrCast(?*anyopaque, @constCast(&hook_block)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @as(?*anyopaque, @ptrCast(@constCast(&hook_block))), null, 1, 0);

// tracing all instruction
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @ptrCast(?*anyopaque, @constCast(&hook_code)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @as(?*anyopaque, @ptrCast(@constCast(&hook_code))), null, 1, 0);

// write machine code to be emulated to memory
try unicorn.uc_mem_write(uc, ADDRESS, RISCV_CODE, RISCV_CODE.len - 1);

// emulate 1 instruction, wrong address, illegal code
unicorn.uc_emu_start(uc, 0x1000, @bitCast(u64, @as(i64, -1)), 0, 1) catch |err|
unicorn.uc_emu_start(uc, 0x1000, @as(u64, @bitCast(@as(i64, -1))), 0, 1) catch |err|
log.err("Expected Illegal Instruction error, got: {} ({s})", .{ err, unicorn.uc_strerror(err) });

// emulate 1 instruction, correct address, valid code
unicorn.uc_emu_start(uc, ADDRESS, @bitCast(u64, @as(i64, -1)), 0, 1) catch |err|
unicorn.uc_emu_start(uc, ADDRESS, @as(u64, @bitCast(@as(i64, -1))), 0, 1) catch |err|
log.err("Failed on uc_emu_start() with error returned: {}", .{err});

// now print out some registers
log.info(">>> Emulation done. Below is the CPU context", .{});

try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @ptrCast(?*anyopaque, @constCast(&a0)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @ptrCast(?*anyopaque, @constCast(&a1)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @as(?*anyopaque, @ptrCast(@constCast(&a0))));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @as(?*anyopaque, @ptrCast(@constCast(&a1))));

log.info(">>> A0 = 0x{}", .{a0});
log.info(">>> A1 = 0x{}", .{a1});
Expand Down Expand Up @@ -127,21 +127,21 @@ fn test_riscv_func_return() !void {
try unicorn.uc_mem_write(uc, ADDRESS, CODE, CODE.len - 1);

// tracing all basic blocks with customized callback
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @ptrCast(?*anyopaque, @constCast(&hook_block)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @as(?*anyopaque, @ptrCast(@constCast(&hook_block))), null, 1, 0);

// tracing all instruction
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @ptrCast(?*anyopaque, @constCast(&hook_code)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @as(?*anyopaque, @ptrCast(@constCast(&hook_code))), null, 1, 0);

ra = 0x10006;
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_RA, @ptrCast(?*anyopaque, @constCast(&ra)));
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_RA, @as(?*anyopaque, @ptrCast(@constCast(&ra))));

log.info("========", .{});
// execute c.ret instruction
unicorn.uc_emu_start(uc, 0x10004, @bitCast(u64, @as(i64, -1)), 0, 1) catch |err| {
unicorn.uc_emu_start(uc, 0x10004, @as(u64, @bitCast(@as(i64, -1))), 0, 1) catch |err| {
log.err("Failed on uc_emu_start() with error returned: {}", .{err});
};

try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_PC, @ptrCast(?*anyopaque, @constCast(&pc)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_PC, @as(?*anyopaque, @ptrCast(@constCast(&pc))));
if (pc != ra) {
log.info("Error after execution: PC is: 0x{}, expected was 0x{}", .{ pc, ra });
if (pc == 0x10004) {
Expand Down Expand Up @@ -180,22 +180,22 @@ fn test_riscv2() !void {
try unicorn.uc_mem_write(uc, ADDRESS, RISCV_CODE, RISCV_CODE.len - 1);

// initialize machine registers
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_A0, @ptrCast(?*anyopaque, @constCast(&a0)));
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_A1, @ptrCast(?*anyopaque, @constCast(&a1)));
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_A0, @as(?*anyopaque, @ptrCast(@constCast(&a0))));
try unicorn.uc_reg_write(uc, unicornC.UC_RISCV_REG_A1, @as(?*anyopaque, @ptrCast(@constCast(&a1))));

// tracing all basic blocks with customized callback
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @ptrCast(?*anyopaque, @constCast(&hook_block)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace1, unicornC.UC_HOOK_BLOCK, @as(?*anyopaque, @ptrCast(@constCast(&hook_block))), null, 1, 0);

// tracing all instruction
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @ptrCast(?*anyopaque, @constCast(&hook_block)), null, 1, 0);
try unicorn.uc_hook_add(uc, &trace2, unicornC.UC_HOOK_CODE, @as(?*anyopaque, @ptrCast(@constCast(&hook_block))), null, 1, 0);

// emulate 1 instruction
unicorn.uc_emu_start(uc, ADDRESS, ADDRESS + 4, 0, 0) catch |err| {
log.err("Failed on unicornC.uc_emu_start() with error returned: {}", .{err});
};

try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @ptrCast(?*anyopaque, @constCast(&a0)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @ptrCast(?*anyopaque, @constCast(&a1)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @as(?*anyopaque, @ptrCast(@constCast(&a0))));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @as(?*anyopaque, @ptrCast(@constCast(&a1))));

log.info(">>> A0 = 0x{}", .{a0});
log.info(">>> A1 = 0x{}", .{a1});
Expand All @@ -208,8 +208,8 @@ fn test_riscv2() !void {
// now print out some registers
log.info(">>> Emulation done. Below is the CPU context", .{});

try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @ptrCast(?*anyopaque, @constCast(&a0)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @ptrCast(?*anyopaque, @constCast(&a1)));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A0, @as(?*anyopaque, @ptrCast(@constCast(&a0))));
try unicorn.uc_reg_read(uc, unicornC.UC_RISCV_REG_A1, @as(?*anyopaque, @ptrCast(@constCast(&a1))));

log.info(">>> A0 = 0x{}", .{a0});
log.info(">>> A1 = 0x{}", .{a1});
Expand Down

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