Idea of this repo came from my own answer(advice) I wrote for a question on quora: VLSI: What are good ways to learn to get better at digital design?. This repository serves as a means to accomplish some of the ways I had discussed in my answer.
The idea for this repository is to therefore build hardware models in Verilog, SystemVerilog, VHDL, SystemC, HLS(C++,OpenCL) at various levels of abstraction: Logic, RTL,TLM and Behavioral/Algorithmic. Also, as much as possible, focus would be to make the hardware models which are:
- Generic, Reusable and Portable
- Built using best practices for design and coding
- Integrable in larger designs through simple handshake interface or as Memory mapped Master/Slave IP on industry standard bus interfaces such as AXI
- Script driven
- C simulation (golden reference stimulus-response generation)
- C/RTL Co-simulation (Pre-Synthesis or RTL Functional Verification using Testbenches )
- IP Export and IP Integration (Memory mapped master/slave)
- Design constraint specification (clock, i/o pin constraints)
- Logic Synthesis
- Post-Synthesis or Gate Level Functional Verification using Testbenches
- Technology Mapping
- Placement and Routing
- Timing Analysis and Closure
- Reporting (waveform dumps, timing, area, power)
- Bit-stream generation and writing bitstream on target FPGA device
- In-circuit testing of design on target FPGA board through JTAG/GPIO ports using signal generators, integrated/external logic analyzers setup as a test-fixture.
- Glue Logic: Register, Shift-Register, Counters, Encoder/Decoder, Mux/Demux, Block RAMs
- IEEE Pipelined Floating Point Fused Multiplier Accumulator Unit (32-bit and 64-bit)
- DSP Algorithms: 2D or 3D FFT, FIR (CIC etc.) and IIR Filters(Biquad IIR etc.)
- Serial Interface or Controllers IP such as I2C, SPI, 16450 UART, SERDES (Serializer Deserializer), Digital PLL
- Bidirectional bus master/slave interfaces(mux or tristate based), Bus arbiter for multiple masters
- Direct Digital Synthesizer(DDS) using external DAC
- Processor Micro-architecture units: Instruction Fetch, Pre-decode, Decode, ALU(scalar and simd vector), Register File, Register R/W, Register Rename, Dispatch, Retire, Branch predictors, Buffers(Instruction, BTB), Queues(Instruction Issue, Load/Store), DMA IP, DRAM Controller(Memory R/W), Cache Controller, Instruction Cache, Data Cache, Scratch pad shared memory, Coherent cache controller
- Pipelined scalar or vector(SIMD) processor based on a RISC ISA such as ARM 7 or RISC-V using above micro-architecture units
- Super-scalar processor using above micro-architecture units
- Algorithms such as sorting, searching, scan, reduction, shuffle, run length encoding, etc.
- Domain specific algorithms such as cryptography(AES, DES), image processing, wireless(OFDM), machine learning, deep learning, scientific computing etc.
- Synthesis: Synopsys Synplify Pro, Xilinx ISE/Vivado, Synopsys Design Compiler (DC)
- Simulation: Mentor Graphics Modelsim, Questasim, Cadence Incisive
- SoC Design Platforms: Xilinx ISE, Xilinx Vivado/HLS/SDK (SDSoC Development Environment), Microsemi Libero SoC
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FPGA Boards
- Digilent Zybo Zynq Z-7010 ARM/FPGA SoC Development Board
- Snickerdoodle Zynq Z-7020 ARM/FPGA SoC Development Board
- Digilent Nexys 3 Xilinx Spartan-6 FPGA Board
- Microsemi SmartFusion Mixed Signal SoC(FPGA with ARM Cortex M3)
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Instruments for Debugging and Measurements
- Digilent JTAG HS3 Programming Cable
- Digilent Analog Discovery Digital/Analog Oscilloscope plus Signal Generator
I will be using some of the parts from my Analog Design and Modeling github project.
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Logic, RTL Design and Computer Architecture (Verilog, System Verilog, Vhdl)
- Digital Design: A Systems Approach by William J. Dally, R. Curtis Harting, Tor M. Aamodt
- RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design by Stuart Sutherland
- Digital Systems Design with SystemVerilog by Mark Zwolinski
- RTL hardware using VHDL by Pong Chu
- Circuit design and simulation with VHDL by Volnei A. Pedroni
- Logic and Computer Design Fundamentals 5th Edition by M. Morris Mano, Charles R. Kime, Tom Martin
- Digital design and Computer Architecture - ARM edition by Harris & Harris
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High Level Synthesis (Algorithms to Architecture)
- VLSI Digital Signal Processing Systems: Design and Implementation by Keshab K. Parhi
- DSP Architecture Design Essentials by Dejan Markovic, Robert W. Brodersen
- Digital Design of Signal Processing Systems by Shoab Ahmed Khan
- A practical introduction to HW/SW codesign 2nd edition by Patrick Schaumont
- High level synthesis Blue book by Michael Fingeroff
- Parallel Programming for FPGAs by Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer
- Xilinx Vivado Design Suite Tutorial - High-Level Synthesis (UG871)
- Xilinx Introduction to FPGA Design with Vivado High-Level Synthesis (UG998)
- Xilinx Vivado Design Suite User Guide - High-Level Synthesis (UG902)
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FPGA System Design
- FPGA Prototyping by VERILOG Examples by Pong Chu
- FPGA Prototyping by VHDL Examples by Pong Chu
- Top-Down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAs by Hubert Kaeslin
- Embedded Systems Design with Platform FPGAs: Principles and Practices by Ron Sass, Andrew G. Schmidt
- Reconfigurable Computing, Volume 1: The Theory and Practice of FPGA-Based Computation (Systems on Silicon) by Scott Hauck et al.
- The Simple Art of SoC Design Closing the Gap between RTL and ESL by Michael Keating
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Topic Specific Books
- FSM in Hardware (VHDL/SystemVerilog) by Volnei A. Pedroni
- Constraining designs for Synthesis and Timing Analysis by Sanjay Churiwala., Sridhar Gangadharan
- Static Timing Analysis for Nanometer Designs A Practical Approach by J. Bhasker, Rakesh Chadha
- High-Speed Serial I/O Made Simple A Designer's Guide with FPGA Applications by Abhijit Athavale, Carl Christensen