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Merge pull request #8 from nananapo/main
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Add inside,outside to operator precedence list
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dalance authored Oct 20, 2024
2 parents bf8830f + 74e2d3e commit c9ff7a8
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Original file line number Diff line number Diff line change
Expand Up @@ -18,4 +18,4 @@ In expression, operator precedence is almost the same as SystemVerilog.
|`&&` |Left | |
|<code>\|\|</code> |Left | |
|`=` `+=` `-=` `*=` `/=` `%=` `&=` `^=` <code>\|=</code> <br> `<<=` `>>=` `<<<=` `>>>=`|None | |
|`{}` |None |Lowest |
|`{}` `inside` `outside` `if` `case` `switch` |None |Lowest |

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