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Merge pull request #883 from veryl-lang/clock_domain_symbol
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Change symbol of clock domain annotation
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@dalance
dalance authored Aug 15, 2024
2 parents e857ab3 + 1ac1401 commit 4a0ab0e
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Showing 11 changed files with 3,651 additions and 3,650 deletions.
176 changes: 88 additions & 88 deletions crates/analyzer/src/tests.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -35,12 +35,12 @@ fn clock_check() {

let code = r#"
module ModuleB (
clk_a: input '_a clock<2>,
clk_b: input '_b clock[2]
clk_a: input `_a clock<2>,
clk_b: input `_b clock[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a[POS]) {
a = 0;
}
Expand All @@ -55,12 +55,12 @@ fn clock_check() {

let code = r#"
module ModuleC (
clk_a: input '_a clock<2, 2>,
clk_b: input '_b clock[2, 2]
clk_a: input `_a clock<2, 2>,
clk_b: input `_b clock[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a[POS][POS]) {
a = 0;
}
Expand Down Expand Up @@ -89,12 +89,12 @@ fn clock_check() {

let code = r#"
module ModuleE (
clk_a: input '_a clock<2>,
clk_b: input '_b clock[2]
clk_a: input `_a clock<2>,
clk_b: input `_b clock[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a) {
a = 0;
}
Expand All @@ -109,12 +109,12 @@ fn clock_check() {

let code = r#"
module ModuleF (
clk_a: input '_a clock<2>,
clk_b: input '_b clock[2]
clk_a: input `_a clock<2>,
clk_b: input `_b clock[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a[POS]) {
a = 0;
}
Expand All @@ -129,12 +129,12 @@ fn clock_check() {

let code = r#"
module ModuleG (
clk_a: input '_a clock<2, 2>,
clk_b: input '_b clock[2, 2]
clk_a: input `_a clock<2, 2>,
clk_b: input `_b clock[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a[POS]) {
a = 0;
}
Expand All @@ -149,12 +149,12 @@ fn clock_check() {

let code = r#"
module ModuleH (
clk_a: input '_a clock<2, 2>,
clk_b: input '_b clock[2, 2]
clk_a: input `_a clock<2, 2>,
clk_b: input `_b clock[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a[POS][POS]) {
a = 0;
}
Expand Down Expand Up @@ -189,14 +189,14 @@ fn reset_check() {

let code = r#"
module ModuleB (
clk_a: input '_a clock,
rst_a: input '_a reset<2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2]
clk_a: input `_a clock,
rst_a: input `_a reset<2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a[POS]) {
if_reset {
a = 0;
Expand All @@ -215,14 +215,14 @@ fn reset_check() {

let code = r#"
module ModuleC (
clk_a: input '_a clock,
rst_a: input '_a reset<2, 2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2, 2]
clk_a: input `_a clock,
rst_a: input `_a reset<2, 2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a[POS][POS]) {
if_reset {
a = 0;
Expand Down Expand Up @@ -258,14 +258,14 @@ fn reset_check() {

let code = r#"
module ModuleE (
clk_a: input '_a clock,
rst_a: input '_a reset<2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2]
clk_a: input `_a clock,
rst_a: input `_a reset<2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a) {
if_reset {
a = 0;
Expand All @@ -284,14 +284,14 @@ fn reset_check() {

let code = r#"
module ModuleF (
clk_a: input '_a clock,
rst_a: input '_a reset<2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2]
clk_a: input `_a clock,
rst_a: input `_a reset<2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a[POS]) {
if_reset {
a = 0;
Expand All @@ -310,14 +310,14 @@ fn reset_check() {

let code = r#"
module ModuleG (
clk_a: input '_a clock,
rst_a: input '_a reset<2, 2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2, 2]
clk_a: input `_a clock,
rst_a: input `_a reset<2, 2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a[POS]) {
if_reset {
a = 0;
Expand All @@ -336,14 +336,14 @@ fn reset_check() {

let code = r#"
module ModuleH (
clk_a: input '_a clock,
rst_a: input '_a reset<2, 2>,
clk_b: input '_b clock,
rst_b: input '_b reset[2, 2]
clk_a: input `_a clock,
rst_a: input `_a reset<2, 2>,
clk_b: input `_b clock,
rst_b: input `_b reset[2, 2]
) {
local POS: u32 = 0;
var a: '_a logic;
var b: '_b logic;
var a: `_a logic;
var b: `_b logic;
always_ff (clk_a, rst_a[POS][POS]) {
if_reset {
a = 0;
Expand Down Expand Up @@ -1048,8 +1048,8 @@ fn missing_clock_signal() {

let code = r#"
module ModuleC (
clk_0: input '_0 clock,
clk_1: input '_1 clock
clk_0: input `_0 clock,
clk_1: input `_1 clock
){
always_ff {}
}
Expand Down Expand Up @@ -1926,9 +1926,9 @@ fn invalid_cast() {
fn clock_domain() {
let code = r#"
module ModuleA (
i_clk: input 'a clock,
i_dat: input 'a logic,
o_dat: output 'b logic,
i_clk: input `a clock,
i_dat: input `a logic,
o_dat: output `b logic,
) {
assign o_dat = i_dat;
}
Expand All @@ -1942,10 +1942,10 @@ fn clock_domain() {

let code = r#"
module ModuleB (
i_clk : input 'a clock,
i_dat0: input 'a logic,
i_dat1: input 'b logic,
o_dat : output 'a logic,
i_clk : input `a clock,
i_dat0: input `a logic,
i_dat1: input `b logic,
o_dat : output `a logic,
) {
assign o_dat = {i_dat0, i_dat1};
}
Expand All @@ -1959,10 +1959,10 @@ fn clock_domain() {

let code = r#"
module ModuleC (
i_clk : input 'a clock,
i_dat0: input 'a logic,
i_dat1: input 'b logic,
o_dat : output 'a logic,
i_clk : input `a clock,
i_dat0: input `a logic,
i_dat1: input `b logic,
o_dat : output `a logic,
) {
inst u: ModuleD (
i_dat: i_dat1,
Expand All @@ -1986,10 +1986,10 @@ fn clock_domain() {

let code = r#"
module ModuleE (
i_clk : input 'a clock,
i_dat0: input 'a logic,
i_dat1: input 'b logic,
o_dat : output 'a logic,
i_clk : input `a clock,
i_dat0: input `a logic,
i_dat1: input `b logic,
o_dat : output `a logic,
) {
inst u: $sv::Module (
i_dat: i_dat1,
Expand All @@ -2006,12 +2006,12 @@ fn clock_domain() {

let code = r#"
module ModuleF (
i_clk : input 'a clock,
i_dat0: input 'a logic,
i_dat1: input 'b logic,
o_dat : output 'b logic,
i_clk : input `a clock,
i_dat0: input `a logic,
i_dat1: input `b logic,
o_dat : output `b logic,
) {
var r_dat: 'b logic;
var r_dat: `b logic;
always_ff {
r_dat = i_dat1;
Expand All @@ -2029,9 +2029,9 @@ fn clock_domain() {

let code = r#"
module ModuleG (
i_clk: input 'a clock,
i_dat: input 'a logic,
o_dat: modport 'b InterfaceA::port,
i_clk: input `a clock,
i_dat: input `a logic,
o_dat: modport `b InterfaceA::port,
) {
assign o_dat.a = i_dat;
}
Expand All @@ -2053,9 +2053,9 @@ fn clock_domain() {

let code = r#"
module ModuleH (
i_clk: input 'a clock,
i_dat: input 'a logic,
o_dat: output 'b logic,
i_clk: input `a clock,
i_dat: input `a logic,
o_dat: output `b logic,
) {
always_comb {
o_dat = i_dat;
Expand Down
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