project namespace

[dalance]

to avoid name conflict between packages

[dalance]

:: can be used for project namespace resolver like package.

[dependencies]
prj1 = { git = "" }

module ModuleA {
    inst a: prj1::ModuleB;
}

In SystemVerilog, :: is replaced with _.

module ModuleA;
    prj1_ModuleB a();
endmodule

[dalance]

Project name should be added too.

[project]
name = "sample"

[dependencies]
prj1 = { git = "" }

module ModuleA {
    inst a: prj1::ModuleB;
}

module sample_ModuleA;
    prj1_ModuleB a();
endmodule