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type cast #48

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dalance opened this issue Dec 27, 2022 · 1 comment
Closed

type cast #48

dalance opened this issue Dec 27, 2022 · 1 comment
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lang Language design

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dalance commented Dec 27, 2022

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@dalance dalance added the lang Language design label Dec 27, 2022
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dalance commented Dec 28, 2022

  • SystemVerilog style
assign a = TYPENAME'(b);
  • Rust style
assign a = b as TYPENAME;

SystemVerilog style is started by typename. It is heavy to parse because token length of typename is not restricted (ex. PATH::PATH::PATH:: [too many path] ::TYPENAME)
So I think Rust style is better.

  • Modified SystemVerilog
assign a = 'TYPENAME(b);

This can be parsed easily. It may be confusable with SystemVerilog.

dalance added a commit that referenced this issue Jan 16, 2023
@dalance dalance closed this as completed Jan 16, 2023
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