Pull request zephyrproject-rtos#7: [HRPN-55] Harpoon release 2.0.0 fo…

…r MCUX_2.10.0

Merge in MCUCORE/mcu-sdk-github from ~NXA27796/mcu-sdk-github:release/MCUX_2.10.0_aarch64_0.1 to main

* commit '722102d4dca4172a6ed547fe940949215c4ccdd0':
  Harpoon release 2.0.0 for MCUX_2.10.0

CMSIS/Core_A/Include/CMSIS_Include_core_ca.cmake

@@ -0,0 +1,12 @@
+#Description: CMSIS Include For Cortex-A; user_visible: True
+include_guard(GLOBAL)
+message("CMSIS_Include_core_ca component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/../Source/mmu_armv8a.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+

CMSIS/Core_A/Include/cmsis_compiler.h

@@ -0,0 +1,92 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V1.0.0
+ * @date     05. october 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Define compiler macros for CPU architecture, if not yet defined by the
+ * compiler default macros
+ */
+#if __ARM_ARCH_8A__
+/* Macro already defined */
+#else
+  #if defined(__ARM_ARCH_8A) && __ARM_ARCH_8A == 1
+    #define __ARM_ARCH_8A__ 1
+  #endif /* __ARM_ARCH_8A == 1 */
+#endif
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iar.h"
+
+#else
+  #error Unknown compiler
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_COMPILER_H */

CMSIS/Core_A/Include/cmsis_gcc.h

@@ -0,0 +1,185 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.0
+ * @date     05. october 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+
+#ifndef __STRINGIFY
+  #define __STRINGIFY(x)                         #x
+#endif
+
+#ifndef __MSR
+  #define __MSR(sysreg, val) \
+    __asm volatile ("msr "__STRINGIFY(sysreg)", %0\n" : : "r"((uint64_t)(val)))
+#endif
+
+#ifndef __MRS
+#define __MRS(sysreg, pVal) \
+  __asm volatile ("mrs  %0, "__STRINGIFY(sysreg)"\n" : "=r"((*pVal)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+
+/**
+  \brief   Get Interrupt Mask Bits
+  \details Returns the current state of the interrupt mask bits from the DAIF register.
+  \return  Interrupt Mask value
+ */
+__STATIC_FORCEINLINE uint64_t __get_DAIF(void)
+{
+    uint64_t result;
+    __MRS(DAIF, &result);
+    return result;
+}
+
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the DAIF.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("msr daifclr, #2" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the DAIF.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("msr daifset, #2" : : : "memory");
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+
+/**
+  \brief   Multiprocessor Affinity
+  \details Indicates the core number in the Cortex-Axx processor.
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR_EL1(void)
+{
+    uint32_t result;
+    __MRS(MPIDR_EL1, &result);
+    return result;
+}
+
+#define MPIDR_GetCoreID() (__get_MPIDR_EL1() & 0xff)
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#ifndef __ISB
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb":::"memory");
+}
+#endif
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#ifndef __DSB
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb sy":::"memory");
+}
+#endif
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#ifndef __DMB
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb sy":::"memory");
+}
+#endif
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("brk "#value)
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+
+__STATIC_FORCEINLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+#endif /* __CMSIS_GCC_H */

CMSIS/Core_A/Include/cmsis_iar.h

@@ -0,0 +1,30 @@
+/**************************************************************************//**
+ * @file     cmsis_iar.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.0
+ * @date     05. october 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CMSIS_IAR_H
+#define __CMSIS_IAR_H
+
+#error Unsupported compiler
+
+#endif /* __CMSIS_IAR_H */