Used to connect different modules and creates path the instruction takes through the processor. You can find the pdf here.
Part of the Control Unit. It is used to set different flags depending on the instruction, that is suppposed to be executed.
You can find the pdf here.
The block folder contains the associated files.
The adder module is fairly straight forward. The adder has two data inputs, adds them together and outputs the result.
The mux module is also quite simple. It has one parameter, which determines the width of the data inputs (d0, d1) and output.
| input logic s | output logic y |
|---|---|
| 0 | d0 |
| 1 | d1 |
The register file module is used by digitial system to store temporary variables. In arm 32-bit, we have 15 32-bit register. You can find the synthesiis of the code here.
The extender module is used to extend different bit-widths. Here is how this functions:
| Imm Src | Ext Imm |
|---|---|
| 00 | Imm {24x0} instr_7:0 |
| 01 | {20x0} instr_11:0 |
| 10 | {6xinstr_23} instr_23:0 |
You can find the pdf here.
The ALU is used to execute various arithmetic calculations. You can find the synthesis here.
- Update README and add all synthesized modules
- Write Testbench
- Depending on Testbench results, fix bugs
- This project is based on the book
Digital Design and Computer Architectureby Harris & Harris and their implementation of a Single-Cycle-Processor. - Im only learning how to optimize with yosys, which is why it is possible, that the synthesized product is a bit blown out of proportion.