Fixes for network core. Both cores booting successfully now.

wolfSSL · Sep 20, 2024 · 7e0e1e7 · 7e0e1e7
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Showing 13 changed files with 240 additions and 56 deletions.
diff --git a/config/examples/nrf5340.config b/config/examples/nrf5340.config
@@ -22,28 +22,27 @@ EXT_FLASH?=1
 SPI_FLASH?=0
 QSPI_FLASH?=1
 
-# Flash is 4KB pages (app) 2KB pages (net)
+# Flash is 4KB pages (app)
 WOLFBOOT_SECTOR_SIZE?=0x1000
 
-# Application Partition Size (1MB-64KB)
-WOLFBOOT_PARTITION_SIZE?=0xF0000
+# Application offset (reserve 48KB for wolfBoot)
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
 
-# Reserve 64KB for wolfBoot
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x10000
+# Application Partition Size (952KB)
+WOLFBOOT_PARTITION_SIZE?=0xEE000
 
-# Flash offset for update (offset 0)
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x00000000
+# External Flash offset for application update (1MB)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0
 
-# Flash offset for network update (offset 1MB)
+# External Flash offset for network update (256KB)
 WOLFBOOT_PARTITION2_UPDATE_ADDRESS?=0x100000
 
-# Flash offset for swap (offset 2MB)
-WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x200000
+# External Flash offset for swap (4KB)
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x140000
 
 V?=0
 DEBUG?=0
 DEBUG_UART?=1
 USE_GCC=1
 
 CFLAGS_EXTRA+=-DDEBUG_FLASH
-
diff --git a/config/examples/nrf5340_net.config b/config/examples/nrf5340_net.config
@@ -7,7 +7,7 @@ WOLFBOOT_VERSION?=1
 VTOR?=1
 CORTEX_M0?=0
 CORTEX_M33?=1
-NO_ASM?=0
+NO_ASM?=1
 NO_MPU=1
 ALLOW_DOWNGRADE?=0
 NVM_FLASH_WRITEONCE?=0
@@ -17,33 +17,32 @@ RAM_CODE?=1
 
 DUALBANK_SWAP?=0
 FLAGS_HOME=0
-DISABLE_BACKUP=1
+DISABLE_BACKUP=0
 EXT_FLASH?=0
 SPI_FLASH?=0
 QSPI_FLASH?=0
 
 # Flash base for network core
 ARCH_FLASH_OFFSET=0x01000000
 
-# Flash is 4KB pages (app) 2KB pages (net)
-WOLFBOOT_SECTOR_SIZE?=0x1000
+# Flash is 2KB pages
+WOLFBOOT_SECTOR_SIZE?=0x800
 
-# Application Partition Size (256KB-64KB)
-WOLFBOOT_PARTITION_SIZE?=0x18000
+# Application offset (reserve 48KB for wolfBoot)
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x0100C000
 
-# Reserve 64KB for wolfBoot
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x01010000
+# Application Partition Size (184KB)
+WOLFBOOT_PARTITION_SIZE?=0x2E000
 
-# Flash offset for update (not used)
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0
+# Flash offset for update (not used - handled by application core)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0100C000
 
-# Flash offset for swap (not used)
-WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0
+# Flash offset for swap (not used - handled by application core)
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x103A800
 
 V?=0
 DEBUG?=0
 DEBUG_UART?=1
 USE_GCC=1
 
 CFLAGS_EXTRA+=-DDEBUG_FLASH
-
diff --git a/docs/Targets.md b/docs/Targets.md
@@ -2135,8 +2135,56 @@ The cores communicate using the IPC peripheral.
 
 The network core can access application core resources (flash, RAM, and peripherals) when granted permission through the application's DCNF and SPU settings. A small portion of the application core RAM is dedicated to the exchange of messages between the application and network cores.
 
+The DK board has two virtual COM ports. Application core and Network core will each output to different VCOM ports.
+
+Example Boot Output:
+
+Application Core:
+
+```
+wolfBoot HAL Init (app core)
+QSPI Freq=24MHz (Div Clk=3/Sck=1), Addr=24-bits, PageSz=256
+QSPI Activate
+QSPI Flash ID (ret 0): 0xC2 0x28 0x17
+Status Reg: Ret 0, 0x40 (Quad Enabled: Yes)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+Boot partition: 0x10000 (size 7376, version 0x1)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 256 , 0x0 -> 0x20000128
+Boot header magic 0xFFFFFFFF invalid at 0x20000128
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+Boot partition: 0x10000 (size 7376, version 0x1)
+Booting version: 0x1
+========================
+nRF5340 wolfBoot (app core)
+Copyright 2024 wolfSSL Inc
+GPL v3
+Version : 0x1
+========================
+Internal Flash Write: addr 0xFDFFC, len 4
+Internal Flash Write: addr 0xFDFFB, len 1
+```
+
+Network Core:
+
+```
+wolfBoot HAL Init (net core)
+Boot partition: 0x100C000 (size 5468, version 0x1)
+Update partition: 0x100C000 (size 5468, version 0x1)
+Boot partition: 0x100C000 (size 5468, version 0x1)
+Booting version: 0x1
+========================
+nRF5340 wolfBoot (network core)
+Copyright 2024 wolfSSL Inc
+GPL v3
+Version : 0x1
+========================
+```
+
 ### Building / Flashing Nordic nRF5340
 
+You may optionally use `./tools/scripts/nrf5340/build_flash.sh` for building and flashing both cores.
+
 #### Application Core
 
 Flash base: 0x00000000, SRAM base: 0x20000000

diff --git a/hal/nrf5340.c b/hal/nrf5340.c
@@ -46,24 +46,37 @@ static int test_flash(void);
 #ifndef UART_SEL
 #define UART_SEL     0 /* select UART 0 or 1 */
 #endif
-
+#if !defined(UART_PORT) && !defined(UART_PIN)
+    #if UART_SEL == 0 && !defined(TARGET_nrf5340_net)
+        #define UART_PORT 0
+        #define UART_PIN  20
+    #else
+        #define UART_PORT 1
+        #define UART_PIN  1
+    #endif
+#endif
+#ifndef UART_PIN
+#define UART_PIN
+#endif
 void uart_init(void)
 {
     /* nRF5340-DK:
-     * App: UART0=P1.01, UART1=P0.20
-     * Net: UART0= */
-
+     * App: UART0=P1.01, UART1=P0.20 */
     UART_ENABLE(UART_SEL) = 0;
-#if UART_SEL == 0
-    GPIO_PIN_CNF(1, 1) = GPIO_CNF_OUT;
-    UART_PSEL_TXD(UART_SEL) = (PSEL_PORT(1) | 1);
-#else
-    GPIO_PIN_CNF(0, 20) = GPIO_CNF_OUT;
-    UART_PSEL_TXD(UART_SEL) = (PSEL_PORT(0) | 20);
-#endif
+    GPIO_PIN_CNF(UART_PORT, UART_PIN) = (GPIO_CNF_OUT
+    #ifdef TARGET_nrf5340_net
+        | GPIO_CNF_MCUSEL(1)
+    #endif
+    );
+    UART_PSEL_TXD(UART_SEL) = (PSEL_PORT(UART_PORT) | UART_PIN);
     UART_BAUDRATE(UART_SEL) = BAUD_115200;
     UART_CONFIG(UART_SEL) = 0; /* Flow=Diabled, Stop=1-bit, Parity exclude */
     UART_ENABLE(UART_SEL) = 8;
+
+    /* allow network core access to P1.01 - must be set from application core */
+#ifdef TARGET_nrf5340_app
+    GPIO_PIN_CNF(1, 1) = (GPIO_CNF_OUT | GPIO_CNF_MCUSEL(1));
+#endif
 }
 
 #ifndef UART_TX_MAX_SZ
@@ -187,10 +200,12 @@ void RAMFUNCTION hal_flash_lock(void)
 
 static void clock_init(void)
 {
+#ifndef TARGET_nrf5340_net
     CLOCK_HFCLKSRC = 1; /* use external high frequency clock */
     CLOCK_HFCLKSTART = 1;
     /* wait for high frequency clock startup */
     while (CLOCK_HFCLKSTARTED == 0);
+#endif
 }
 
 void sleep_us(unsigned int us)
@@ -209,13 +224,24 @@ void sleep_us(unsigned int us)
     }
 }
 
+/* Stringification */
+#ifndef WC_STRINGIFY
+#define _WC_STRINGIFY_L2(str) #str
+#define WC_STRINGIFY(str) _WC_STRINGIFY_L2(str)
+#endif
+
 void hal_init(void)
 {
     clock_init();
 
+#ifdef TARGET_nrf5340_app
+    /* stop the network core from booting */
+    NETWORK_FORCEOFF = NETWORK_FORCEOFF_HOLD;
+#endif
+
 #ifdef DEBUG_UART
     uart_init();
-    uart_write("wolfBoot HAL Init\n", 18);
+    uart_write("wolfBoot HAL Init (" CORE_STR " core)\n", 29);
 #endif
 
 #ifdef TEST_FLASH
@@ -227,7 +253,16 @@ void hal_init(void)
 
 void hal_prepare_boot(void)
 {
-
+#ifdef TARGET_nrf5340_app
+    /* release network core - errata 161 network core release */
+    NETWORK_ERRATA_161 = 1;
+    NETWORK_FORCEOFF = NETWORK_FORCEOFF_RELEASE;
+    sleep_us(5);
+    NETWORK_FORCEOFF = NETWORK_FORCEOFF_HOLD;
+    sleep_us(1);
+    NETWORK_FORCEOFF = NETWORK_FORCEOFF_RELEASE;
+    NETWORK_ERRATA_161 = 0;
+#endif
 }
 
 /* Test for internal flash erase/write */

diff --git a/hal/nrf5340.h b/hal/nrf5340.h
@@ -27,15 +27,18 @@
 #ifdef TARGET_nrf5340_net
     /* Network core */
     #undef QSPI_FLASH /* not supported on network core */
+    #define CORE_STR "net"
 #else
     /* Application core */
+    #define TARGET_nrf5340_app
+    #define CORE_STR "app"
     #ifndef TZEN
         /* at reset/power on wolfBoot is using secure bases */
         #define TZEN
     #endif
 #endif
 
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
 #define CPU_CLOCK 128000000UL /* 128MHz */
 #else
 #define CPU_CLOCK  64000000UL /*  64MHz */
@@ -54,7 +57,7 @@ void sleep_us(unsigned int us);
 #define PSEL_PORT(n)         (((n) & 0x1) << 5)
 
 /* Domain Configuration */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define DCNF_BASE (0x50000000)
     #else
@@ -65,7 +68,7 @@ void sleep_us(unsigned int us);
 #endif
 
 #define DCNF_CPUID         *((volatile uint32_t *)(DCNF_BASE + 0x420))
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     /* allows blocking of network cores ability to resources on application core */
     #define DCNF_EXTPERI0_PROT *((volatile uint32_t *)(DCNF_BASE + 0x440))
     #define DCNF_EXTRAM0_PROT  *((volatile uint32_t *)(DCNF_BASE + 0x460)) /* Eight 64KB slaves bit 0=0x20000000-0x20010000 (64KB) */
@@ -76,7 +79,7 @@ void sleep_us(unsigned int us);
 #define UICR_BASE (0x00FF8000UL)
 
 /* Reset */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define RESET_BASE (0x50005000)
     #else
@@ -94,10 +97,11 @@ void sleep_us(unsigned int us);
 #define NETWORK_FORCEOFF  *((volatile uint32_t *)(RESET_BASE + 0x614))
 #define NETWORK_FORCEOFF_RELEASE 0
 #define NETWORK_FORCEOFF_HOLD    1
+#define NETWORK_ERRATA_161 *((volatile uint32_t *)(RESET_BASE + 0x618))
 
 
 /* Non-volatile memory controller */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define NVMC_BASE (0x50039000)
     #else
@@ -123,7 +127,7 @@ void sleep_us(unsigned int us);
 #define FLASH_PAGE_SIZE (4096)
 
 /* Clock control */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define CLOCK_BASE  (0x50005000)
     #else
@@ -154,7 +158,7 @@ void sleep_us(unsigned int us);
 
 
 /* GPIO Port (0-1) */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define GPIO_BASE(n) (0x50842500 + (((n) & 0x1) * 0x300))
     #else
@@ -182,7 +186,7 @@ void sleep_us(unsigned int us);
 #define GPIO_CNF_MCUSEL(n)   (((n) & 0x7) << 28)
 
 /* UART (0-1) */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
     #else
@@ -208,7 +212,7 @@ void sleep_us(unsigned int us);
 void uart_write_sz(const char* c, unsigned int sz);
 
 /* SPI (0-2) */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define SPI_BASE(n)  (0x50008000 + (((n) & 0x3) * 0x1000))
     #else
@@ -245,7 +249,7 @@ void uart_write_sz(const char* c, unsigned int sz);
 #define SPI_FREQ_M32  0x14000000
 
 /* QSPI */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
         #define QSPI_BASE         (0x5002B000)
     #else
@@ -327,7 +331,7 @@ void uart_write_sz(const char* c, unsigned int sz);
 #endif
 
 /* interprocessor communication (IPC) peripheral */
-#ifdef TARGET_nrf5340
+#ifdef TARGET_nrf5340_app
     #ifdef TZEN
     #define IPC_BASE      (0x5002A000)
     #else