Support for the Nordic nRF5340 (application and network cores):

* Added nRF5340 driver support for Clock, Internal Flash (NVMC), GPIO, SPU, OTP, UART, SPI, QSPI and IPC.
* Added support for updating the network core (Sign using "--id 2")/
* Cleanup the nRF52 port
* Improved external QSPI and internal Flash tests and logging.
* Improved internal printf support for formatter length.

.gdbinit

@@ -1,6 +1,7 @@
 tar rem:3333
 file wolfboot.elf
 add-symbol-file test-app/image.elf
+set pagination off
 foc c
 
 

.github/workflows/test-configs.yml

@@ -116,6 +116,18 @@ jobs:
       arch: arm
       config-file: ./config/examples/nrf52840.config
 
+  nrf5340_app_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/nrf5340.config
+
+  nrf5340_net_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/nrf5340_net.config
+
   nxp_p1021_test:
     uses: ./.github/workflows/test-build.yml
     with:

arch.mk

@@ -181,7 +181,9 @@ ifeq ($(CORTEX_M33),1)
   CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
   LDFLAGS+=-mcpu=cortex-m33
   ifeq ($(TZEN),1)
-    OBJS+=hal/stm32_tz.o
+    ifneq (,$(findstring stm32,$(TARGET)))
+      OBJS+=hal/stm32_tz.o
+    endif
     CFLAGS+=-mcmse
     ifeq ($(WOLFCRYPT_TZ),1)
       SECURE_OBJS+=./src/wc_callable.o

config/examples/nrf52840.config

@@ -3,6 +3,7 @@ TARGET?=nrf52
 SIGN?=ECC256
 HASH?=SHA256
 DEBUG?=0
+DEBUG_UART?=1
 VTOR?=1
 CORTEX_M0?=0
 NO_ASM?=0

config/examples/nrf5340.config

@@ -0,0 +1,47 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=nrf5340
+SIGN?=ECC256
+HASH?=SHA256
+WOLFBOOT_VERSION?=1
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+
+SPMATH?=1
+RAM_CODE?=1
+
+DUALBANK_SWAP?=0
+FLAGS_HOME=0
+DISABLE_BACKUP=0
+EXT_FLASH?=1
+SPI_FLASH?=0
+QSPI_FLASH?=1
+
+# Flash is 4KB pages (app)
+WOLFBOOT_SECTOR_SIZE?=0x1000
+
+# Application offset (reserve 48KB for wolfBoot)
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
+
+# Application Partition Size (952KB)
+WOLFBOOT_PARTITION_SIZE?=0xEE000
+
+# External Flash offset for application update (1MB)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0
+
+# External Flash offset for network update at 0x100000 (size=256KB)
+
+# External Flash offset for swap (4KB)
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x140000
+
+V?=0
+DEBUG?=0
+DEBUG_UART?=1
+USE_GCC=1
+
+CFLAGS_EXTRA+=-DDEBUG_FLASH

config/examples/nrf5340_net.config

@@ -0,0 +1,48 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=nrf5340_net
+SIGN?=ECC256
+HASH?=SHA256
+WOLFBOOT_VERSION?=1
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=1
+NO_MPU=1
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+
+SPMATH?=1
+RAM_CODE?=1
+
+DUALBANK_SWAP?=0
+FLAGS_HOME=0
+DISABLE_BACKUP=0
+EXT_FLASH?=0
+SPI_FLASH?=0
+QSPI_FLASH?=0
+
+# Flash base for network core
+ARCH_FLASH_OFFSET=0x01000000
+
+# Flash is 2KB pages
+WOLFBOOT_SECTOR_SIZE?=0x800
+
+# Application offset (reserve 48KB for wolfBoot)
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x0100C000
+
+# Application Partition Size (184KB)
+WOLFBOOT_PARTITION_SIZE?=0x2E000
+
+# Flash offset for update (not used - handled by application core)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0100C000
+
+# Flash offset for swap (not used - handled by application core)
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x103A800
+
+V?=0
+DEBUG?=0
+DEBUG_UART?=1
+USE_GCC=1
+
+CFLAGS_EXTRA+=-DDEBUG_FLASH

docs/Targets.md

@@ -4,24 +4,27 @@ This README describes configuration of supported targets.
 
 ## Supported Targets
 
+* [Simulated](#simulated)
 * [Cortex-A53 / Raspberry PI 3](#cortex-a53--raspberry-pi-3-experimental)
 * [Cypress PSoC-6](#cypress-psoc-6)
 * [Infineon AURIX TC3xx](#infineon-aurix-tc3xx)
 * [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support)
 * [Microchip SAME51](#microchip-same51)
+* [Nordic nRF52840](#nordic-nrf52840)
+* [Nordic nRF5340](#nordic-nrf5340)
+* [NXP iMX-RT](#nxp-imx-rt)
 * [NXP Kinetis](#nxp-kinetis)
 * [NXP LPC54xxx](#nxp-lpc54xxx)
 * [NXP MCXA153](#nxp-mcxa153)
 * [NXP P1021 PPC](#nxp-qoriq-p1021-ppc)
 * [NXP T1024 PPC](#nxp-qoriq-t1024-ppc)
 * [NXP T2080 PPC](#nxp-qoriq-t2080-ppc)
-* [NXP iMX-RT](#nxp-imx-rt)
-* [Nordic nRF52840](#nordic-nrf52840)
 * [Qemu x86-64 UEFI](#qemu-x86-64-uefi)
 * [Renesas RA6M4](#renesas-ra6m4)
 * [Renesas RX65N](#renesas-rx65n)
 * [Renesas RX72N](#renesas-rx72n)
 * [Renesas RZN2L](#renesas-rzn2l)
+* [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
 * [STM32C0](#stm32c0)
 * [STM32F4](#stm32f4)
 * [STM32F7](#stm32f7)
@@ -33,7 +36,6 @@ This README describes configuration of supported targets.
 * [STM32L5](#stm32l5)
 * [STM32U5](#stm32u5)
 * [STM32WB55](#stm32wb55)
-* [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
 * [TI Hercules TMS570LC435](#ti-hercules-tms570lc435)
 * [Xilinx Zynq UltraScale](#xilinx-zynq-ultrascale)
 
@@ -2122,6 +2124,135 @@ Example of flash memory layout and configuration on the nRF52:
 #define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x58000
 ```
 
+
+## Nordic nRF5340
+
+Tested with the Nordic nRF5340-DK. This device has two cores:
+1) Application core: Cortex-M33 at 128MHz, w/TrustZone, 1MB flash, 512KB RAM
+2) Network core: Cortex-M33 at 64MHz, 256KB Flash and 64KB RAM
+
+The cores communicate using the IPC peripheral.
+
+The network core can access application core resources (flash, RAM, and peripherals) when granted permission through the application's DCNF and SPU settings. A small portion of the application core RAM is dedicated to the exchange of messages between the application and network cores.
+
+The DK board has two virtual COM ports. Application core and Network core will each output to different VCOM ports.
+
+Example Boot Output:
+
+Application Core:
+
+```
+wolfBoot HAL Init (app core)
+QSPI Freq=24MHz (Div Clk=3/Sck=1), Addr=24-bits, PageSz=256
+QSPI Activate
+QSPI Flash ID (ret 0): 0xC2 0x28 0x17
+Status Reg: Ret 0, 0x40 (Quad Enabled: Yes)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+Boot partition: 0xC000 (size 7428, version 0x1)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 256 , 0x0 -> 0x20000128
+Update partition: 0x0 (size 7428, version 0x2)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 4 , 0xEDFFC -> 0x2000022C
+Boot partition: 0xC000 (size 7428, version 0x1)
+Booting version: 0x1
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 256 , 0x100000 -> 0x20000128
+Update partition: 0x100000 (size 5492, version 0x2)
+QSPI Flash Read: Ret 0, Cmd 0xEB, Len 256 , 0x0 -> 0x20000230
+Network version: 0x2
+========================
+nRF5340 wolfBoot (app core)
+Copyright 2024 wolfSSL Inc
+GPL v3
+Version : 0x1
+========================
+Internal Flash Write: addr 0xF9FFC, len 4
+Internal Flash Write: addr 0xF9FFB, len 1
+```
+
+Network Core:
+
+```
+wolfBoot HAL Init (net core)
+Boot partition: 0x100C000 (size 5492, version 0x1)
+Update partition: 0x100C000 (size 5492, version 0x1)
+Boot partition: 0x100C000 (size 5492, version 0x1)
+Booting version: 0x1
+========================
+nRF5340 wolfBoot (net core)
+Copyright 2024 wolfSSL Inc
+GPL v3
+Version : 0x1
+========================
+Internal Flash Write: addr 0x1039FFC, len 4
+Internal Flash Write: addr 0x1039FFB, len 1
+```
+
+### Building / Flashing Nordic nRF5340
+
+You may optionally use `./tools/scripts/nrf5340/build_flash.sh` for building and flashing both cores.
+
+The `nrfjprog` can be used to program external QSPI flash for testing. Example: `nrfjprog --program <qspi_content.hex> --verify -f nrf53`
+
+#### Application Core
+
+Flash base: 0x00000000, SRAM base: 0x20000000
+
+Building Application core:
+
+```sh
+cp config/examples/nrf5340.config .config
+make clean
+make
+```
+
+Flashing Application core with JLink:
+
+```
+JLinkExe -device nRF5340_xxAA_APP -if SWD -speed 4000 -jtagconf -1,-1 -autoconnect 1
+loadbin factory.bin 0x0
+rnh
+```
+
+#### Network Core
+
+Flash base: 0x01000000, SRAM base: 0x21000000
+
+Building Network core:
+
+```sh
+cp config/examples/nrf5340_net.config .config
+make clean
+make
+```
+
+Flashing Network core with JLink:
+
+```
+JLinkExe -device nRF5340_xxAA_NET -if SWD -speed 4000 -jtagconf -1,-1 -autoconnect 1
+loadbin factory.bin 0x01000000
+rnh
+```
+
+### Debugging Nordic nRF5340
+
+Debugging with JLink:
+
+1) Start GDB Server:
+```
+JLinkGDBServer -device nRF5340_xxAA_APP -if SWD -port 3333
+```
+
+2) Start GDB
+This will use .gdbinit, but can supply `wolfboot.elf -ex "target remote localhost:3333"` if permissions not allowing.
+
+```
+arm-none-eabi-gdb
+b main
+mon reset
+c
+```
+
+
 ## Simulated
 
 You can create a simulated target that uses files to mimic an internal and
@@ -2864,8 +2995,8 @@ repository that can be directly flashed into the BIOS flash of the board.
 
 ## Infineon AURIX TC3xx
 
-wolfBoot supports the AURIX TC3xx family of devices, and provides a demo application targeting the TC375 AURIX LiteKit-V2. 
+wolfBoot supports the AURIX TC3xx family of devices, and provides a demo application targeting the TC375 AURIX LiteKit-V2.
 
-For detailed instructions on using wolfBoot with the AURIX TC3xx, please refer to [IDE/AURIX/README.md](../IDE/AURIX/README.md)  
+For detailed instructions on using wolfBoot with the AURIX TC3xx, please refer to [IDE/AURIX/README.md](../IDE/AURIX/README.md)
 
-wolfBoot can also integrate with [wolfHSM](https://www.wolfssl.com/products/wolfhsm/) on AURIX TC3xx devices, offloading cryptographic operations and key storage to the AURIX HSM core. For more information on using wolfBoot with wolfHSM on AURIX devices, please contact us at facts@wolfssl.com. 
+wolfBoot can also integrate with [wolfHSM](https://www.wolfssl.com/products/wolfhsm/) on AURIX TC3xx devices, offloading cryptographic operations and key storage to the AURIX HSM core. For more information on using wolfBoot with wolfHSM on AURIX devices, please contact us at facts@wolfssl.com.

hal/nrf52.c

@@ -19,32 +19,42 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 
+#ifdef TARGET_nrf52
+
 #include <stdint.h>
 #include "image.h"
+#include "nrf52.h"
 
-/* Assembly helpers */
-#define DMB() __asm__ volatile ("dmb")
-
-
-/* Instantiation */
-#define CLOCK_CONTROL_BASE (0x40000000)
-#define NVMC_BASE (0x4001E000)
-
+#ifdef DEBUG_UART
+void uart_init(void)
+{
+    UART0_BAUDRATE = BAUD_115200;
+    UART0_ENABLE = 1;
+}
 
-/* Flash write/erase control */
-#define NVMC_CONFIG *((volatile uint32_t *)(NVMC_BASE + 0x504))
-#define NVMC_ERASEPAGE *((volatile uint32_t *)(NVMC_BASE + 0x508))
-#define NVMC_READY *((volatile uint32_t *)(NVMC_BASE + 0x400))
-#define NVMC_CONFIG_REN 0
-#define NVMC_CONFIG_WEN 1
-#define NVMC_CONFIG_EEN 2
+static void uart_write_char(char c)
+{
+    UART0_EVENT_ENDTX = 0;
 
-#define FLASH_PAGE_SIZE (4096)
+    UART0_TXD_PTR = (uint32_t)(&c);
+    UART0_TXD_MAXCOUNT = 1;
+    UART0_TASK_STARTTX = 1;
+    while(UART0_EVENT_ENDTX == 0)
+        ;
+}
 
-/* Clock control */
-#define TASKS_HFCLKSTART   *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x000))
-#define TASKS_HFCLKSTOP    *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x004))
-#define TASKS_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x100))
+void uart_write(const char* buf, unsigned int sz)
+{
+    uint32_t pos = 0;
+    while (sz-- > 0) {
+        char c = buf[pos++];
+        if (c == '\n') { /* handle CRLF */
+            uart_write_char('\r');
+        }
+        uart_write_char(c);
+    }
+}
+#endif /* DEBUG_UART */
 
 static void RAMFUNCTION flash_wait_complete(void)
 {
@@ -117,3 +127,4 @@ void hal_prepare_boot(void)
     TASKS_HFCLKSTOP = 1;
 }
 
+#endif /* TARGET_nrf52 */