mcux: hal_nxp: Update from mcux-sdk to include MKE1XZ9

Update the mcux-sdk to pull in MKE1XZ9 and various patches. Signed-off-by: David Leach <david.leach@nxp.com>
zephyrproject-rtos · Apr 25, 2024 · 8c354a9 · 8c354a9
1 parent cd046fa
commit 8c354a9
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diff --git a/mcux/README b/mcux/README
@@ -4,7 +4,7 @@ MCUXpresso SDK
 Origin:
    NXP MCUXpresso SDK
    https://github.com/nxp-mcuxpresso/mcux-sdk
-   SHA: acc105f1e6304bf3a16ebbb503f8882a4daa1408
+   SHA: a6bf851f65020c437704e53d2d9587ae21789d65
 
    NXP Kinetis Connectivity Software
    https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&Parent_nodeId=1432854896956716810497&Parent_pageType=product
@@ -68,15 +68,4 @@ Patch List:
      - All *.a binary archive files. Files are still present in the SDK github repo but are not allowed in Zephyr Project
      - mcux-sdk\manifests
      - mcux-sdk\docs
-  4. Add RW61X device_system.cmake
-  5. devices: MCXN947: Update system file to remove SDK sepecific defines
-  6. devices: MIMX8UD7: add header and source files for HIFI4 DSP core
-  7. devices: MIMX8UD7: fsl_device_registers.h: add support for HIFI4 DSP
-  8. devices: MIMX8UD7: add cmake file for reset driver
-  9. drivers: lpflexcomm: lpi2c: Fixed an error in the driver when interacting with the lpflexcomm driver
-  10. devices: LPC5534: Changed FSL_FEATURE_PWM_HAS_NO_WAITEN from 1 to 0 to solve pwm issue.
-  11. devices: LPC5536: Changed FSL_FEATURE_PWM_HAS_NO_WAITEN from 1 to 0 to solve pwm issue.
-  12. devices: LPC55S36: Changed FSL_FEATURE_PWM_HAS_NO_WAITEN from 1 to 0 to solve pwm issue.
-  13. devices: MIMX8UD7: add definition for LPUART_RX_TX_IRQS
-  14. devices: MCXN947: clock: Updated the clock frequency, case 3 on GetWdtClkFreq returns 1MHZ
-  15. devices: MIMX8UD7: add soc layer definitions required for using EDMA rev2
+  4. devices: MCXN947: clock: Updated the clock frequency, case 3 on GetWdtClkFreq returns 1MHZ
diff --git a/mcux/mcux-sdk/SW-Content-Register.txt b/mcux/mcux-sdk/SW-Content-Register.txt
diff --git a/mcux/mcux-sdk/boards/rdrw612bga/board.c b/mcux/mcux-sdk/boards/rdrw612bga/board.c
@@ -108,7 +108,7 @@ status_t BOARD_InitPsRam(void)
     flexspi_device_config_t psramConfig = {
         .flexspiRootClk       = 320000000, /* 320MHZ SPI serial clock, DDR serial clock 160M */
         .isSck2Enabled        = false,
-        .flashSize            = 0x1000, /* 32Mb/KByte */
+        .flashSize            = 0x1000,    /* 32Mb/KByte */
         .addressShift         = true,
         .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
         .CSInterval           = 5,
@@ -144,7 +144,7 @@ status_t BOARD_InitPsRam(void)
         /* Read Register */
         [8]  = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0xCC, kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x00),
         [9]  = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16, kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD,
-                              16),
+                               16),
         [10] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_4PAD, 12, kFLEXSPI_Command_READ_DDR, kFLEXSPI_4PAD,
                                0x01),
 

diff --git a/mcux/mcux-sdk/boards/rdrw612bga/board.h b/mcux/mcux-sdk/boards/rdrw612bga/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2022 NXP
+ * Copyright 2021-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -8,7 +8,6 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
-#include "clock_config.h"
 #include "fsl_common.h"
 #include "fsl_gpio.h"
 
@@ -120,7 +119,7 @@
 #define BOARD_SMARTCARD_MODULE                (USIM)      /*!< SMARTCARD communicational module instance */
 #define BOARD_SMARTCARD_MODULE_IRQ            (USIM_IRQn) /*!< SMARTCARD communicational module IRQ handler */
 #define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetUsimClkFreq())
-#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U) /*!< SMARTCARD clock frequency (4Mhz) */
+#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U)  /*!< SMARTCARD clock frequency (4Mhz) */
 #define BOARD_SMARTCARD_IRQ_PORT              (0)
 #define BOARD_SMARTCARD_IRQ_PIN               (19)
 #define BOARD_SMARTCARD_TS_TIMER_IRQ          (CTIMER0_IRQn)

diff --git a/mcux/mcux-sdk/boards/rdrw612bga/flash_config/flash_config.h b/mcux/mcux-sdk/boards/rdrw612bga/flash_config/flash_config.h
@@ -192,6 +192,9 @@ typedef struct _fc_flexspi_mem_config
  */
 typedef struct _fc_flexspi_nor_config
 {
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+    uint8_t padding[0x400];            /* !< Padding for MDK and IAR */
+#endif
     fc_flexspi_mem_config_t memConfig; /* !< Common memory configuration info via FlexSPI */
     uint32_t pageSize;                 /* !< Page size of Serial NOR */
     uint32_t sectorSize;               /* !< Sector size of Serial NOR */

diff --git a/mcux/mcux-sdk/boards/rdrw612bga/set_board_rdrw612bga.cmake b/mcux/mcux-sdk/boards/rdrw612bga/set_board_rdrw612bga.cmake
@@ -0,0 +1,40 @@
+include_guard(GLOBAL)
+
+
+if (CONFIG_USE_BOARD_Project_Template_rdrw612bga)
+# Add set(CONFIG_USE_BOARD_Project_Template_rdrw612bga true) in config.cmake to use this component
+
+message("BOARD_Project_Template_rdrw612bga component is included from ${CMAKE_CURRENT_LIST_FILE}.")
+
+if((CONFIG_BOARD STREQUAL rdrw612bga) AND CONFIG_USE_component_usart_adapter AND (CONFIG_DEVICE_ID STREQUAL RW612) AND CONFIG_USE_device_RW612_startup AND CONFIG_USE_driver_cache_cache64 AND CONFIG_USE_driver_clock AND CONFIG_USE_driver_cns_io_mux AND CONFIG_USE_driver_common AND CONFIG_USE_driver_flash_config_rdrw612bga AND CONFIG_USE_driver_flexcomm_usart AND CONFIG_USE_driver_flexspi AND CONFIG_USE_driver_lpc_gpio AND CONFIG_USE_driver_power AND CONFIG_USE_driver_reset AND CONFIG_USE_driver_ocotp AND CONFIG_USE_component_els_pkc_platform_rw61x_standalone_clib_gdet_sensor AND ((CONFIG_USE_component_serial_manager AND CONFIG_USE_utility_assert AND CONFIG_USE_utility_debug_console) OR (CONFIG_USE_utility_assert_lite AND CONFIG_USE_utility_debug_console_lite)))
+
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.h "" BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.c "" BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.c "" BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.c "" BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_rdrw612bga)
+add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.c "" BOARD_Project_Template_rdrw612bga)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/project_template/.
+)
+
+if(CONFIG_USE_COMPONENT_CONFIGURATION)
+  message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}")
+
+  target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC
+    -DFSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1
+  )
+
+endif()
+
+else()
+
+message(SEND_ERROR "BOARD_Project_Template_rdrw612bga dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.")
+
+endif()
+
+endif()
+
diff --git a/mcux/mcux-sdk/cmsis_drivers/uart/fsl_uart_cmsis.c b/mcux/mcux-sdk/cmsis_drivers/uart/fsl_uart_cmsis.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
  * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
- * Copyright 2016-2017,2020,2021 NXP. Not a Contribution.
+ * Copyright 2016-2017,2020,2021,2023 NXP. Not a Contribution.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -25,11 +25,172 @@
 #define FSL_COMPONENT_ID "platform.drivers.uart_cmsis"
 #endif
 
+#if (FSL_FEATURE_SOC_LPUART_COUNT == 3) && (FSL_FEATURE_SOC_UART_COUNT == 2)
+#ifdef RTE_USART0
+#undef RTE_USART0
+#endif
+#ifdef RTE_USART0_DMA_EN
+#undef RTE_USART0_DMA_EN
+#endif
+#ifdef RTE_USART0_DMA_TX_CH
+#undef RTE_USART0_DMA_TX_CH
+#endif
+#ifdef RTE_USART0_DMA_TX_PERI_SEL
+#undef RTE_USART0_DMA_TX_PERI_SEL
+#endif
+#ifdef RTE_USART0_DMA_TX_DMAMUX_BASE
+#undef RTE_USART0_DMA_TX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART0_DMA_TX_DMA_BASE
+#undef RTE_USART0_DMA_TX_DMA_BASE
+#endif
+#ifdef RTE_USART0_DMA_RX_CH
+#undef RTE_USART0_DMA_RX_CH
+#endif
+#ifdef RTE_USART0_DMA_RX_PERI_SEL
+#undef RTE_USART0_DMA_RX_PERI_SEL
+#endif
+#ifdef RTE_USART0_DMA_RX_DMAMUX_BASE
+#undef RTE_USART0_DMA_RX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART0_DMA_RX_DMA_BASE
+#undef RTE_USART0_DMA_RX_DMA_BASE
+#endif
+#ifdef USART0_RX_BUFFER_ENABLE
+#undef USART0_RX_BUFFER_ENABLE
+#endif
+#ifdef RTE_USART0_PIN_INIT
+#undef RTE_USART0_PIN_INIT
+#endif
+#ifdef RTE_USART0_PIN_DEINIT
+#undef RTE_USART0_PIN_DEINIT
+#endif
+
+#ifdef RTE_USART1
+#undef RTE_USART1
+#endif
+#ifdef RTE_USART1_DMA_EN
+#undef RTE_USART1_DMA_EN
+#endif
+#ifdef RTE_USART1_DMA_TX_CH
+#undef RTE_USART1_DMA_TX_CH
+#endif
+#ifdef RTE_USART1_DMA_TX_PERI_SEL
+#undef RTE_USART1_DMA_TX_PERI_SEL
+#endif
+#ifdef RTE_USART1_DMA_TX_DMAMUX_BASE
+#undef RTE_USART1_DMA_TX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART1_DMA_TX_DMA_BASE
+#undef RTE_USART1_DMA_TX_DMA_BASE
+#endif
+#ifdef RTE_USART1_DMA_RX_CH
+#undef RTE_USART1_DMA_RX_CH
+#endif
+#ifdef RTE_USART1_DMA_RX_PERI_SEL
+#undef RTE_USART1_DMA_RX_PERI_SEL
+#endif
+#ifdef RTE_USART1_DMA_RX_DMAMUX_BASE
+#undef RTE_USART1_DMA_RX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART1_DMA_RX_DMA_BASE
+#undef RTE_USART1_DMA_RX_DMA_BASE
+#endif
+#ifdef USART1_RX_BUFFER_ENABLE
+#undef USART1_RX_BUFFER_ENABLE
+#endif
+#ifdef RTE_USART1_PIN_INIT
+#undef RTE_USART1_PIN_INIT
+#endif
+#ifdef RTE_USART1_PIN_DEINIT
+#undef RTE_USART1_PIN_DEINIT
+#endif
+
+#ifdef RTE_USART3
+#define RTE_USART0 RTE_USART3
+#endif
+#ifdef RTE_USART3_DMA_EN
+#define RTE_USART0_DMA_EN RTE_USART3_DMA_EN
+#endif
+#ifdef RTE_USART3_DMA_TX_CH
+#define RTE_USART0_DMA_TX_CH RTE_USART3_DMA_TX_CH
+#endif
+#ifdef RTE_USART3_DMA_TX_PERI_SEL
+#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART3_DMA_TX_PERI_SEL
+#endif
+#ifdef RTE_USART3_DMA_TX_DMAMUX_BASE
+#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART3_DMA_TX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART3_DMA_TX_DMA_BASE
+#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART3_DMA_TX_DMA_BASE
+#endif
+#ifdef RTE_USART3_DMA_RX_CH
+#define RTE_USART0_DMA_RX_CH RTE_USART3_DMA_RX_CH
+#endif
+#ifdef RTE_USART3_DMA_RX_PERI_SEL
+#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART3_DMA_RX_PERI_SEL
+#endif
+#ifdef RTE_USART3_DMA_RX_DMAMUX_BASE
+#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART3_DMA_RX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART3_DMA_RX_DMA_BASE
+#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART3_DMA_RX_DMA_BASE
+#endif
+#ifdef USART3_RX_BUFFER_ENABLE
+#define USART0_RX_BUFFER_ENABLE USART3_RX_BUFFER_ENABLE
+#endif
+#ifdef RTE_USART3_PIN_INIT
+#define RTE_USART0_PIN_INIT RTE_USART3_PIN_INIT
+#endif
+#ifdef RTE_USART3_PIN_DEINIT
+#define RTE_USART0_PIN_DEINIT RTE_USART3_PIN_DEINIT
+#endif
+
+#ifdef RTE_USART4
+#define RTE_USART1 RTE_USART4
+#endif
+#ifdef RTE_USART4_DMA_EN
+#define RTE_USART1_DMA_EN RTE_USART4_DMA_EN
+#endif
+#ifdef RTE_USART4_DMA_TX_CH
+#define RTE_USART1_DMA_TX_CH RTE_USART4_DMA_TX_CH
+#endif
+#ifdef RTE_USART4_DMA_TX_PERI_SEL
+#define RTE_USART1_DMA_TX_PERI_SEL RTE_USART4_DMA_TX_PERI_SEL
+#endif
+#ifdef RTE_USART4_DMA_TX_DMAMUX_BASE
+#define RTE_USART1_DMA_TX_DMAMUX_BASE RTE_USART4_DMA_TX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART4_DMA_TX_DMA_BASE
+#define RTE_USART1_DMA_TX_DMA_BASE RTE_USART4_DMA_TX_DMA_BASE
+#endif
+#ifdef RTE_USART4_DMA_RX_CH
+#define RTE_USART1_DMA_RX_CH RTE_USART4_DMA_RX_CH
+#endif
+#ifdef RTE_USART4_DMA_RX_PERI_SEL
+#define RTE_USART1_DMA_RX_PERI_SEL RTE_USART4_DMA_RX_PERI_SEL
+#endif
+#ifdef RTE_USART4_DMA_RX_DMAMUX_BASE
+#define RTE_USART1_DMA_RX_DMAMUX_BASE RTE_USART4_DMA_RX_DMAMUX_BASE
+#endif
+#ifdef RTE_USART4_DMA_RX_DMA_BASE
+#define RTE_USART1_DMA_RX_DMA_BASE RTE_USART4_DMA_RX_DMA_BASE
+#endif
+#ifdef USART4_RX_BUFFER_ENABLE
+#define USART1_RX_BUFFER_ENABLE USART4_RX_BUFFER_ENABLE
+#endif
+#ifdef RTE_USART4_PIN_INIT
+#define RTE_USART1_PIN_INIT RTE_USART4_PIN_INIT
+#endif
+#ifdef RTE_USART4_PIN_DEINIT
+#define RTE_USART1_PIN_DEINIT RTE_USART4_PIN_DEINIT
+#endif
+#endif
 #if ((defined(RTE_USART0) && RTE_USART0 && defined(UART0)) || (defined(RTE_USART1) && RTE_USART1 && defined(UART1)) || \
      (defined(RTE_USART2) && RTE_USART2 && defined(UART2)) || (defined(RTE_USART3) && RTE_USART3 && defined(UART3)) || \
      (defined(RTE_USART4) && RTE_USART4 && defined(UART4)) || (defined(RTE_USART5) && RTE_USART5 && defined(UART5)))
 
-#define ARM_UART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (1))
+#define ARM_UART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (2))
 
 /*
  * ARMCC does not support split the data section automatically, so the driver
@@ -1386,8 +1547,11 @@ static ARM_USART_STATUS UART0_NonBlockingGetStatus(void)
 }
 
 #endif
-
+#if ((FSL_FEATURE_SOC_LPUART_COUNT == 3) && (FSL_FEATURE_SOC_UART_COUNT == 2))
+ARM_DRIVER_USART Driver_USART3 = {
+#else
 ARM_DRIVER_USART Driver_USART0 = {
+#endif
     UARTx_GetVersion,      UARTx_GetCapabilities,
 #if defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN
 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
@@ -1697,7 +1861,11 @@ static ARM_USART_STATUS UART1_NonBlockingGetStatus(void)
 
 #endif
 
+#if ((FSL_FEATURE_SOC_LPUART_COUNT == 3) && (FSL_FEATURE_SOC_UART_COUNT == 2))
+ARM_DRIVER_USART Driver_USART4 = {
+#else
 ARM_DRIVER_USART Driver_USART1 = {
+#endif
     UARTx_GetVersion,      UARTx_GetCapabilities,
 #if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN
 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)

diff --git a/mcux/mcux-sdk/cmsis_drivers/uart/fsl_uart_cmsis.h b/mcux/mcux-sdk/cmsis_drivers/uart/fsl_uart_cmsis.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
  * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
- * Copyright 2016-2017,2020 NXP. Not a Contribution.
+ * Copyright 2016-2017,2020,2023 NXP. Not a Contribution.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -59,6 +59,15 @@ extern ARM_DRIVER_USART Driver_USART4;
 extern ARM_DRIVER_USART Driver_USART5;
 #endif /* UART5 */
 
+#if (FSL_FEATURE_SOC_LPUART_COUNT == 3) && (FSL_FEATURE_SOC_UART_COUNT == 2)
+#if defined(UART0) && defined(RTE_USART3) && RTE_USART3
+extern ARM_DRIVER_USART Driver_USART3;
+#endif /* UART0 */
+#if defined(UART1) && defined(RTE_USART4) && RTE_USART4
+extern ARM_DRIVER_USART Driver_USART4;
+#endif /* UART1 */
+#endif
+
 /* USART Driver state flags */
 #define USART_FLAG_UNINIT     (0UL)
 #define USART_FLAG_INIT       (1UL << 0)

diff --git a/mcux/mcux-sdk/components/adc_sensor/fsl_adapter_adc_sensor.h b/mcux/mcux-sdk/components/adc_sensor/fsl_adapter_adc_sensor.h
@@ -17,9 +17,9 @@
  * Public macro
  ******************************************************************************/
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_ADC_SENSOR_ADAPTER_VERSION (MAKE_VERSION(1, 0, 0)) /*!< Version 1.0.0. */
-/*@}*/
+/*! @} */
 
 /*! @brief Definition of ADC_SENSOR adapter handle size. */
 #define HAL_ADC_SENSOR_HANDLE_SIZE (64U)