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tests/crypto/test_ecc_dsa intermittently fails on riscv32 #3461

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zephyrbot opened this issue Apr 11, 2017 · 1 comment
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tests/crypto/test_ecc_dsa intermittently fails on riscv32 #3461

zephyrbot opened this issue Apr 11, 2017 · 1 comment
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area: RISCV RISCV Architecture (32-bit & 64-bit) area: Security Security bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug
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@zephyrbot
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zephyrbot commented Apr 11, 2017

Reported by Andrew Boie:

qemu_riscv32              tests/crypto/test_ecc_dsa/test                     FAILED: failed
------------------sanity-out/qemu_riscv32/tests/crypto/test_ecc_dsa/test/qemu.log-------------------
***** BOOTING ZEPHYR OS v1.7.99 - BUILD: Apr 11 2017 19:45:23 *****
tc_start() - TinyCrypt ECC DSA test

  Vector <span>#</span>00 check sig.r - FAILURE
[FAIL] Test <span>#</span>1: ECDSAsign - NIST-p256, SHA2-256
===================================================================
FAIL - main.
===================================================================
PROJECT EXECUTION FAILED
------------------sanity-out/qemu_riscv32/tests/crypto/test_ecc_dsa/test/qemu.log-------------------

This issue was undetected for a while as the test case was only enabled on x86/ARM.
This is an intermittent failure, not 100% reproducible. It may be timing-related.

(Imported from Jira ZEP-2020)

@zephyrbot
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zephyrbot commented Jun 30, 2017

by Jean-Paul Etienne:

Merged in zephyr master
commit b31b416
Issue fixed by commit "riscv32: fixed context restore upon exiting ISR"

Jira: GH-3461

Signed-off-by: Jean-Paul Etienne fractalclone@gmail.com

commit 3486265
riscv32: fixed context restore upon exiting ISR

By now, t0 register restored value is overwritten
by mepc and mstatus values prior to returning from ISR.

Fixed by restoring mstatus and mepc registers before
restoring the caller-saved registers.

As t0 is a temporary register within the riscv ABI,
this issue was unnoticed for most applications, except
for computation intensive apps, like crypto tests.

Signed-off-by: Jean-Paul Etienne fractalclone@gmail.com

@zephyrbot zephyrbot added priority: low Low impact/importance bug area: RISCV RISCV Architecture (32-bit & 64-bit) area: Security Security bug The issue is a bug, or the PR is fixing a bug labels Sep 23, 2017
@zephyrbot zephyrbot added this to the v1.8.x milestone Sep 23, 2017
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Labels
area: RISCV RISCV Architecture (32-bit & 64-bit) area: Security Security bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug
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