spi: add SPI driver for STM32 family

arch/arm/soc/atmel_sam/same70/soc_config.c

@@ -22,7 +22,7 @@
  */
 static int atmel_same70_config(struct device *dev)
 {
-#ifdef SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
+#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
 	/* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */
 	MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
 #endif

arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c

@@ -15,7 +15,7 @@ static struct nxp_mpu_region mpu_regions[] = {
 	MPU_REGION_ENTRY("DEBUGGER_0",
 			 0,
 			 0xFFFFFFFF,
-			 0),
+			 REGION_DEBUG_ATTR),
 	/* Region 1 */
 	MPU_REGION_ENTRY("FLASH_0",
 			 CONFIG_FLASH_BASE_ADDRESS,

arch/arm/soc/st_stm32/stm32f3/soc.h

@@ -57,6 +57,7 @@ enum stm32f3x_pin_config_mode {
 #include <stm32f3xx_ll_bus.h>
 #include <stm32f3xx_ll_rcc.h>
 #include <stm32f3xx_ll_system.h>
+#include <stm32f3xx_ll_spi.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 #endif /* !_ASMLANGUAGE */

arch/arm/soc/st_stm32/stm32f4/soc.h

@@ -57,6 +57,7 @@ enum stm32f4x_pin_config_mode {
 #include <stm32f4xx_ll_bus.h>
 #include <stm32f4xx_ll_rcc.h>
 #include <stm32f4xx_ll_system.h>
+#include <stm32f4xx_ll_spi.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 #endif /* !_ASMLANGUAGE */

arch/arm/soc/st_stm32/stm32f4/soc_pinmux.c

@@ -112,6 +112,27 @@ static const stm32_pin_func_t pin_pa3_funcs[] = {
 	PINMUX_UART(PA3, UART2, RX)
 };
 
+/* SPI 1*/
+static const stm32_pin_func_t pin_pa4_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PA4_SPI1_NSS - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pa5_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PA5_SPI1_SCK - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pa6_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PA6_SPI1_MISO - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pa7_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
 static const stm32_pin_func_t pin_pa8_funcs[] = {
 	PINMUX_UART(PA8, UART7, RX)
 };
@@ -180,10 +201,24 @@ static const stm32_pin_func_t pin_pb11_funcs[] = {
 
 static const stm32_pin_func_t pin_pb12_funcs[] = {
 	PINMUX_UART(PB12, UART5, RX)
+	[STM32F4_PINMUX_FUNC_PB12_SPI2_NSS - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
 };
 
 static const stm32_pin_func_t pin_pb13_funcs[] = {
 	PINMUX_UART(PB13, UART5, TX)
+	[STM32F4_PINMUX_FUNC_PB13_SPI2_SCK - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pb14_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PB14_SPI2_MISO - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pb15_funcs[] = {
+	[STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI - 1] =
+			STM32F4X_PIN_CONFIG_AF_PUSH_PULL,
 };
 
 /* Port C */
@@ -325,6 +360,10 @@ static const struct stm32_pinmux_conf pins[] = {
 	STM32_PIN_CONF(STM32_PIN_PA1, pin_pa1_funcs),
 	STM32_PIN_CONF(STM32_PIN_PA2, pin_pa2_funcs),
 	STM32_PIN_CONF(STM32_PIN_PA3, pin_pa3_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA4, pin_pa4_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA5, pin_pa5_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA6, pin_pa6_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA7, pin_pa7_funcs),
 	STM32_PIN_CONF(STM32_PIN_PA8, pin_pa8_funcs),
 	STM32_PIN_CONF(STM32_PIN_PA9, pin_pa9_funcs),
 	STM32_PIN_CONF(STM32_PIN_PA10, pin_pa10_funcs),
@@ -344,6 +383,8 @@ static const struct stm32_pinmux_conf pins[] = {
 	STM32_PIN_CONF(STM32_PIN_PB11, pin_pb11_funcs),
 	STM32_PIN_CONF(STM32_PIN_PB12, pin_pb12_funcs),
 	STM32_PIN_CONF(STM32_PIN_PB13, pin_pb13_funcs),
+	STM32_PIN_CONF(STM32_PIN_PB14, pin_pb14_funcs),
+	STM32_PIN_CONF(STM32_PIN_PB15, pin_pb15_funcs),
 
 	/* Port C */
 	STM32_PIN_CONF(STM32_PIN_PC5, pin_pc5_funcs),

arch/arm/soc/st_stm32/stm32l4/soc.h

@@ -40,6 +40,7 @@
 #include <stm32l4xx_ll_bus.h>
 #include <stm32l4xx_ll_rcc.h>
 #include <stm32l4xx_ll_system.h>
+#include <stm32l4xx_ll_spi.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 #endif /* !_ASMLANGUAGE */

arch/arm/soc/ti_lm3s6965/soc.h

@@ -78,8 +78,6 @@ extern "C" {
 /* uart configuration settings */
 #if defined(CONFIG_UART_STELLARIS)
 
-#define UART_IRQ_FLAGS 0
-
 #define UART_STELLARIS_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
 
 #endif /* CONFIG_UART_STELLARIS */

arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Kconfig.defconfig.series - TI SimpleLink CC2650
+#
+
+if SOC_SERIES_CC2650
+
+config SOC_SERIES
+	default cc2650
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 48000000
+
+config NUM_IRQS
+	default 34
+
+endif # SOC_SERIES_CC2650

arch/arm/soc/ti_simplelink/cc2650/Kconfig.series

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Kconfig.series - TI SimpleLink CC2650
+#
+
+config  SOC_SERIES_CC2650
+	bool "TI SimpleLink Family CC2650"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_TISIMPLELINK
+	select CPU_HAS_SYSTICK
+	help
+	  Enable support for TI SimpleLink CC2650.

arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Kconfig.soc - Texas Instruments CC2650
+#
+
+choice
+prompt "TI SimpleLink MCU Selection"
+depends on SOC_SERIES_CC2650
+
+config SOC_CC2650
+	bool "CC2650"
+
+endchoice
+
+if SOC_SERIES_CC2650
+
+config TI_CCFG_PRESENT
+	bool
+	default y
+
+endif # SOC_SERIES_CC2650

arch/arm/soc/ti_simplelink/cc2650/Makefile

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+obj-y += soc.o