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NXP: LPC: various cleanups #24368
NXP: LPC: various cleanups #24368
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galak
commented
Apr 15, 2020
- cleanup and refactoring of LPC55S6x and LPC54xxx device trees
- Remove stale Kconfig options related to LPC support
- Get lpcxpresso55s69_ns building
- Move to nodelabel's for pinmux enablement
As the SRAMs are part of the SoC put the nodes under the SoC container node. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix various board files and nxp_lpc55S6x_ns.dtsi to get the non-secure config building. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move sram nodes under soc as it is for most SoC dts files. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the majority of the device tree into nxp_lpc55S6x_common.dtsi and use ranges to handle the different address may for non-secure. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
All checks passed. checkpatch (informational only, not a failure)
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@@ -204,12 +204,14 @@ | |||
status = "disabled"; | |||
}; | |||
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flexcomm8: flexcomm@9f000 { | |||
compatible = "nxp,lpc-flexcomm"; | |||
hs_lspi: spi@9f000 { |
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where did the "l" come from?
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its what is used in the NXP HAL. hs_lspi/hs_spi seem to be intermixed.
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The flexcomm at 0x9f000 is a high speed SPI interface only. Tweak the device tree to reflect that. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
GPIO2/GPIO3 don't exist on the lpc55s6x so remove these nodes and associated aliases. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CONFIG_GPIO_MCUX_LPC_PORT0_NAME and CONFIG_GPIO_MCUX_LPC_PORT1_NAME aren't used anywhere so we can just remove them. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move board pinmux.c code to utilize DT_NODELABEL instead. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixes #24439 |