boards: fix the sys ticks per second for emsk

[vonhust]

As a slow FPGA platform with max. freq < 25 Mhz,
the default CON_SYS_CLOCK_TICKS_PER_SEC=10000 is
not suitable, will bring some failures in sanitycheck tests(tests/kernel/timer/timer_api, tests/kernel/sched/schedule_api) . CON_SYS_CLOCK_TICKS_PER_SEC=100 is
a better value.

Signed-off-by: Wayne Ren wei.ren@synopsys.com

Fixes #25511

[abrodkin]

Looking at how that config option is defined in kernel/Kconfig I'm not sure we do the right thing here.
So here's the definition:

config SYS_CLOCK_TICKS_PER_SEC
	int "System tick frequency (in ticks/second)"
	default 100 if QEMU_TARGET || SOC_POSIX
	default 10000 if TICKLESS_CAPABLE
	default 100

See SYS_CLOCK_TICKS_PER_SEC is only set to that higher 10.000 value if the timer used is TICKLESS_CAPABLE, otherwise we default to 100 (which we enforce in this patch).

That said don't we want to disable TICKLESS_CAPABLE for such a slow FPGA-based platfrom instead?
I.e. add a condition like that (though I guess this example is not technically correct):

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2c7fdf2c47..3a7d1a1cf9 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -98,7 +98,7 @@ menuconfig ARCV2_TIMER
        bool "ARC Timer"
        default y
        depends on ARC
-       select TICKLESS_CAPABLE
+       select TICKLESS_CAPABLE if !BOARD_EM_STARTERKIT
        help
          This module implements a kernel device driver for the ARCv2 processor timer 0
          and provides the standard "system clock driver" interfaces.

But something along the lines.

Now if we look at other ARC boards we may see this:

boards/arc/emsdp/emsdp_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em4_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em5d_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em6_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em7d_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em7d_esp_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/emsdp/emsdp_em9d_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/hsdk/hsdk_defconfig:6:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/nsim/nsim_em_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/nsim/nsim_hs_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/nsim/nsim_hs_smp_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/nsim/nsim_sem_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig:7:CONFIG_SYS_CLOCK_TICKS_PER_SEC=100

So even HSDK has CONFIG_SYS_CLOCK_TICKS_PER_SEC force set to 100.
The same goes to nSIM platform - is that exactly what we want?

[ruuddw]

Tickless makes sense (even more) for FPGA/slower targets. The problem for this test is that it assumes two timer related function calls can be made within one tick period. That's not realistic in this case, so it makes sense to increase the tick period (10k ticks @25mhz -> 2500 cycles for 1 period; with userspace syscall overhead, locking etc. that's simply not enough).

100 is on the safe side for TICKLESS, imho 1000 would be a better, maybe 5000 works as well.

As Alexey points out, a consistent similar definition for the other ARC boards would be good.

[vonhust]

@ruuddw is right, we can enable TICKLESS for simulators, 1000 or 10000 can improve the accuracy of timeout. The root cause is the tests which assume some operation should be finished in one tick, that's possible for high-freq targets like iotdk/hsdk, but too fast for slow targets, especially for emsk+ddr ram +userspace (BTW: iotdk also may fail, if slow memory is used)

I think 100 ticks per second is a safe value to cover different cases

[abrodkin]

LGTM after discussion and explanation in this thread.

[ruuddw]

100 is safe, 1000 would be better for testing/accuracy (might catch issues on timer accuracy problems).
As this is a bugfix, please add an issue and appropriate labels to get this in 2.3.