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dts: arm: Fix incorrect interrupt cells order #25514

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Abhishek-brcm
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@Abhishek-brcm Abhishek-brcm commented May 21, 2020

In aarch64 DTs, priority and flags cells have been swapped,
fix the same.

Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;

Signed-off-by: Abhishek Shah abhishek.shah@broadcom.com

Fixes #25477

In aarch64 DTs, priority and flags cells have been swapped,
fix the same.

Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
@carlescufi carlescufi added this to the v2.3.0 milestone May 21, 2020
@stephanosio stephanosio added area: Architectures area: ARM ARM (32-bit) Architecture area: Devicetree bug The issue is a bug, or the PR is fixing a bug labels May 21, 2020
@carlescufi carlescufi merged commit f156057 into zephyrproject-rtos:master May 21, 2020
@Abhishek-brcm Abhishek-brcm deleted the arm64_dt_intr_prop_fix branch May 21, 2020 12:59
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@carlocaione @Abhishek-brcm So, this somehow broke QEMU special key handling for qemu_cortex_a53. It seems to be causing whichever thread is responsible for handling the special key inputs to hang/be stuck (e.g. when you press CTRL+a, a key sequence, QEMU should exit, but that doesn't work after the changes in this commit; same goes for CTRL+a c that is supposed to bring up console).

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area: Architectures area: ARM ARM (32-bit) Architecture area: Devicetree bug The issue is a bug, or the PR is fixing a bug
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dts: arm: Incorrect GIC interrupt spec order for AArch64 SoCs
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