[In Progress] feature: Porting mcuboot to Cortex-M0 with no VTOR support

arch/arm/core/CMakeLists.txt

@@ -15,6 +15,7 @@ zephyr_sources(
 zephyr_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
 zephyr_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
 zephyr_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
+zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M0 irq_relay.S)
 
 add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
 add_subdirectory_ifdef(CONFIG_CPU_HAS_MPU  cortex_m/mpu)

arch/arm/core/cortex_m/Kconfig

@@ -50,6 +50,14 @@ config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
 	  This option signifies the CPU faults other than the hard fault, and
 	  needs to reserve a priority for them.
 
+config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option signifies the Cortex-M0 has some mechanisms that can map
+	  the vector table to SRAM
+
 config ARMV6_M
 	bool
 	# Omit prompt to signify "hidden" option
@@ -182,4 +190,13 @@ config ZERO_LATENCY_IRQS
 	  Note that this is a somewhat dangerous option: ISRs of priority zero
 	  interrupts cannot use any kernel functionality.
 
+config SW_VECTOR_RELAY
+	bool
+	prompt "Enable Cortex-M0 Vector Table soft relay"
+	default n
+	depends on CPU_CORTEX_M0 && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	help
+	  Add Cortex-M0 Vector Table relay handler and relay vector table, to
+	  relay interrupts based on a vector table pointer.
+
 endmenu

arch/arm/core/cortex_m/prep_c.c

@@ -26,13 +26,19 @@
 
 #ifdef CONFIG_ARMV6_M
 
+#if defined(CONFIG_SW_VECTOR_RELAY)
+_GENERIC_SECTION(.vt_pointer_section) void *_vector_table_pointer;
+#endif
+
 #define VECTOR_ADDRESS 0
 void __weak relocate_vector_table(void)
 {
 #if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
     !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
 	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
 	memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
+#elif defined(CONFIG_SW_VECTOR_RELAY)
+	_vector_table_pointer = _vector_start;
 #endif
 }
 

arch/arm/core/irq_relay.S

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 Ding Tao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file irq_relay.S
+ *
+ * @brief IRQ relay vector table and relay handler for Cortex-M0 SoC
+ *
+ * In Cortex-M0, the vector table address can not be changed. Once the
+ * vector table is occupied by bootloader, there will be no IRQ support
+ * in chainloaded image.
+ *
+ * This program will link into bootloader, once an interrupt is coming,
+ * bootloader can forward the interrupt to the chainloaded image. This
+ * will support DFU on Cortex-M0 plantform.
+ *
+ * Note: Currently support mcuboot only.
+ * */
+
+#include <board.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <drivers/system_timer.h>
+
+_ASM_FILE_PROLOGUE
+
+#if defined(CONFIG_SW_VECTOR_RELAY)
+
+GDATA(_vector_table_pointer)
+GDATA(_main_stack)
+
+SECTION_FUNC(vector_relay_handler, __vector_relay_handler)
+	mrs		r0, ipsr;
+	lsls	r0, r0, $0x02;
+
+	ldr		r1, = _vector_table_pointer;
+	ldr		r1, [r1];
+	adds	r1, r1, r0;
+	ldr		r1, [r1];
+
+	/**
+	 * The size of IRQ vector is 4 bytes, the offset within vector table
+	 * is the IRQ number times 4 (aka r0 << 2). As know as the r1 stored
+	 * the offset of real vector table, thus the (r1 = r1 + r0 << 2) will
+	 * be the real irq handle vector.
+	 * */
+
+	bx		r1;
+
+GTEXT(__vector_relay_handler)
+
+SECTION_FUNC(vector_relay_table, __vector_relay_table)
+	.word _main_stack + CONFIG_MAIN_STACK_SIZE
+
+	.word __reset
+
+	.word __vector_relay_handler	/* nmi */
+	.word __vector_relay_handler	/* hard fault */
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler	/* svc */
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler	/* pendsv */
+	.word __vector_relay_handler
+	/* End of system exception */
+
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+	.word __vector_relay_handler
+
+#endif

arch/arm/soc/st_stm32/stm32f0/Kconfig.series

@@ -9,6 +9,7 @@ config SOC_SERIES_STM32F0X
 	bool "STM32F0x Series MCU"
 	select CPU_CORTEX_M
 	select CPU_CORTEX_M0
+	select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
 	select SOC_FAMILY_STM32
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	select CPU_HAS_SYSTICK

include/arch/arm/cortex_m/scripts/linker.ld

@@ -95,6 +95,14 @@ SECTIONS
 	KEEP(*(".dbghdr.*"))
 #endif
 	. = CONFIG_TEXT_SECTION_OFFSET;
+
+#if defined(CONFIG_SW_VECTOR_RELAY)
+	KEEP(*(.vector_relay_table))
+	KEEP(*(".vector_relay_table.*"))
+	KEEP(*(.vector_relay_handler))
+	KEEP(*(".vector_relay_handler.*"))
+#endif
+
 	_vector_start = .;
 	KEEP(*(.exc_vector_table))
 	KEEP(*(".exc_vector_table.*"))
@@ -184,6 +192,7 @@ SECTIONS
 
     GROUP_START(RAMABLE_REGION)
 
+
 #if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)
     /* Must be first in ramable region */
 	SECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)
@@ -194,6 +203,15 @@ SECTIONS
 	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 #endif
 
+#if defined(CONFIG_SW_VECTOR_RELAY)
+	/* Reserved 4 bytes to save vector table base address */
+	SECTION_PROLOGUE(.vt_pointer,(NOLOAD),)
+	{
+		*(.vt_pointer_section)
+		*(".vt_pointer_section.*")
+	}
+#endif
+
 #ifdef CONFIG_APPLICATION_MEMORY
 	SECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)
 	{