… modules

Signed-off-by: Dante Su <dante.su@broadcom.com>

…nd revert the clock of FPGA-I2C to high-speed

Signed-off-by: Dante Su <dante.su@broadcom.com>

…ecoder

Signed-off-by: Dante Su <dante.su@broadcom.com>

It's a known issue that Eoptolink CMIS3 requires a software reset after
re-insertion, and a burst of software reset messages observed when its
state != ModuleReady for 5 seconds.

And hence, we'll have the following changes in this commit

1. Update the checker from (state != ModuleReady) to (state == ModuleLowPwr),
   which is exactly the behavior observed on the Eoptolink CMIS3, and its state
   will become ModulePwrDn after reset.
2. Add 1-second delay to the software reset, and hence it's impossible to have
   a burst of reset at a time
3. Ensure the failure counter gets reset when its state != ModuleLowPwr

Signed-off-by: Dante Su <dante.su@broadcom.com>