stage2: basic support for parameters .debug_info

see #6014
ziglang · Aug 12, 2020 · 8282f42 · 8282f42
1 parent a2a5cea
commit 8282f42
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Showing 10 changed files with 491 additions and 96 deletions.
diff --git a/src-self-hosted/Module.zig b/src-self-hosted/Module.zig
@@ -1301,14 +1301,16 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
                 for (fn_proto.params()) |param, i| {
                     const name_token = param.name_token.?;
                     const src = tree.token_locs[name_token].start;
-                    const param_name = tree.tokenSlice(name_token);
-                    const arg = try gen_scope_arena.allocator.create(zir.Inst.NoOp);
+                    const param_name = tree.tokenSlice(name_token); // TODO: call identifierTokenString
+                    const arg = try gen_scope_arena.allocator.create(zir.Inst.Arg);
                     arg.* = .{
                         .base = .{
                             .tag = .arg,
                             .src = src,
                         },
-                        .positionals = .{},
+                        .positionals = .{
+                            .name = param_name,
+                        },
                         .kw_args = .{},
                     };
                     gen_scope.instructions.items[i] = &arg.base;
@@ -1934,6 +1936,20 @@ pub fn addBinOp(
     return &inst.base;
 }
 
+pub fn addArg(self: *Module, block: *Scope.Block, src: usize, ty: Type, name: [*:0]const u8) !*Inst {
+    const inst = try block.arena.create(Inst.Arg);
+    inst.* = .{
+        .base = .{
+            .tag = .arg,
+            .ty = ty,
+            .src = src,
+        },
+        .name = name,
+    };
+    try block.instructions.append(self.gpa, &inst.base);
+    return &inst.base;
+}
+
 pub fn addBr(
     self: *Module,
     scope_block: *Scope.Block,
@@ -2535,7 +2551,7 @@ pub fn coerce(self: *Module, scope: *Scope, dest_type: Type, inst: *Inst) !*Inst
         }
     }
 
-    return self.fail(scope, inst.src, "expected {}, found {}", .{  dest_type, inst.ty });
+    return self.fail(scope, inst.src, "expected {}, found {}", .{ dest_type, inst.ty });
 }
 
 pub fn storePtr(self: *Module, scope: *Scope, src: usize, ptr: *Inst, uncasted_value: *Inst) !*Inst {

diff --git a/src-self-hosted/codegen.zig b/src-self-hosted/codegen.zig
diff --git a/src-self-hosted/codegen/riscv64.zig b/src-self-hosted/codegen/riscv64.zig
@@ -1,4 +1,5 @@
 const std = @import("std");
+const DW = std.dwarf;
 
 pub const instructions = struct {
     pub const CallBreak = packed struct {
@@ -48,6 +49,10 @@ pub const RawRegister = enum(u8) {
     x8,  x9,  x10, x11, x12, x13, x14, x15,
     x16, x17, x18, x19, x20, x21, x22, x23,
     x24, x25, x26, x27, x28, x29, x30, x31,
+
+    pub fn dwarfLocOp(reg: RawRegister) u8 {
+        return @enumToInt(reg) + DW.OP_reg0;
+    }
 };
 
 pub const Register = enum(u8) {
@@ -83,6 +88,10 @@ pub const Register = enum(u8) {
         }
         return null;
     }
+
+    pub fn dwarfLocOp(reg: Register) u8 {
+        return @enumToInt(reg) + DW.OP_reg0;
+    }
 };
 
 // zig fmt: on

diff --git a/src-self-hosted/codegen/x86.zig b/src-self-hosted/codegen/x86.zig
@@ -1,3 +1,6 @@
+const std = @import("std");
+const DW = std.dwarf;
+
 // zig fmt: off
 pub const Register = enum(u8) {
     // 0 through 7, 32-bit registers. id is int value
@@ -37,8 +40,84 @@ pub const Register = enum(u8) {
             else => null,
         };
     }
+
+    /// Convert from any register to its 32 bit alias.
+    pub fn to32(self: Register) Register {
+        return @intToEnum(Register, @as(u8, self.id()));
+    }
+
+    /// Convert from any register to its 16 bit alias.
+    pub fn to16(self: Register) Register {
+        return @intToEnum(Register, @as(u8, self.id()) + 8);
+    }
+
+    /// Convert from any register to its 8 bit alias.
+    pub fn to8(self: Register) Register {
+        return @intToEnum(Register, @as(u8, self.id()) + 16);
+    }
+
+
+    pub fn dwarfLocOp(reg: Register) u8 {
+        return switch (reg.to32()) {
+            .eax => DW.OP_reg0,
+            .ecx => DW.OP_reg1,
+            .edx => DW.OP_reg2,
+            .ebx => DW.OP_reg3,
+            .esp => DW.OP_reg4,
+            .ebp => DW.OP_reg5,
+            .esi => DW.OP_reg6,
+            .edi => DW.OP_reg7,
+            else => unreachable,
+        };
+    }
 };
 
 // zig fmt: on
 
 pub const callee_preserved_regs = [_]Register{ .eax, .ecx, .edx, .esi, .edi };
+
+// TODO add these to Register enum and corresponding dwarfLocOp
+//  // Return Address register. This is stored in `0(%esp, "")` and is not a physical register.
+//  RA = (8, "RA"),
+//
+//  ST0 = (11, "st0"),
+//  ST1 = (12, "st1"),
+//  ST2 = (13, "st2"),
+//  ST3 = (14, "st3"),
+//  ST4 = (15, "st4"),
+//  ST5 = (16, "st5"),
+//  ST6 = (17, "st6"),
+//  ST7 = (18, "st7"),
+//
+//  XMM0 = (21, "xmm0"),
+//  XMM1 = (22, "xmm1"),
+//  XMM2 = (23, "xmm2"),
+//  XMM3 = (24, "xmm3"),
+//  XMM4 = (25, "xmm4"),
+//  XMM5 = (26, "xmm5"),
+//  XMM6 = (27, "xmm6"),
+//  XMM7 = (28, "xmm7"),
+//
+//  MM0 = (29, "mm0"),
+//  MM1 = (30, "mm1"),
+//  MM2 = (31, "mm2"),
+//  MM3 = (32, "mm3"),
+//  MM4 = (33, "mm4"),
+//  MM5 = (34, "mm5"),
+//  MM6 = (35, "mm6"),
+//  MM7 = (36, "mm7"),
+//
+//  MXCSR = (39, "mxcsr"),
+//
+//  ES = (40, "es"),
+//  CS = (41, "cs"),
+//  SS = (42, "ss"),
+//  DS = (43, "ds"),
+//  FS = (44, "fs"),
+//  GS = (45, "gs"),
+//
+//  TR = (48, "tr"),
+//  LDTR = (49, "ldtr"),
+//
+//  FS_BASE = (93, "fs.base"),
+//  GS_BASE = (94, "gs.base"),
diff --git a/src-self-hosted/codegen/x86_64.zig b/src-self-hosted/codegen/x86_64.zig
@@ -1,4 +1,6 @@
+const std = @import("std");
 const Type = @import("../Type.zig");
+const DW = std.dwarf;
 
 // zig fmt: off
 
@@ -101,6 +103,30 @@ pub const Register = enum(u8) {
     pub fn to8(self: Register) Register {
         return @intToEnum(Register, @as(u8, self.id()) + 48);
     }
+
+    pub fn dwarfLocOp(self: Register) u8 {
+        return switch (self.to64()) {
+            .rax => DW.OP_reg0,
+            .rdx => DW.OP_reg1,
+            .rcx => DW.OP_reg2,
+            .rbx => DW.OP_reg3,
+            .rsi => DW.OP_reg4,
+            .rdi => DW.OP_reg5,
+            .rbp => DW.OP_reg6,
+            .rsp => DW.OP_reg7,
+
+            .r8 => DW.OP_reg8,
+            .r9 => DW.OP_reg9,
+            .r10 => DW.OP_reg10,
+            .r11 => DW.OP_reg11,
+            .r12 => DW.OP_reg12,
+            .r13 => DW.OP_reg13,
+            .r14 => DW.OP_reg14,
+            .r15 => DW.OP_reg15,
+
+            else => unreachable,
+        };
+    }
 };
 
 // zig fmt: on
@@ -109,3 +135,86 @@ pub const Register = enum(u8) {
 pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
 pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
 pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
+
+// TODO add these registers to the enum and populate dwarfLocOp
+//    // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
+//    RA = (16, "RA"),
+//
+//    XMM0 = (17, "xmm0"),
+//    XMM1 = (18, "xmm1"),
+//    XMM2 = (19, "xmm2"),
+//    XMM3 = (20, "xmm3"),
+//    XMM4 = (21, "xmm4"),
+//    XMM5 = (22, "xmm5"),
+//    XMM6 = (23, "xmm6"),
+//    XMM7 = (24, "xmm7"),
+//
+//    XMM8 = (25, "xmm8"),
+//    XMM9 = (26, "xmm9"),
+//    XMM10 = (27, "xmm10"),
+//    XMM11 = (28, "xmm11"),
+//    XMM12 = (29, "xmm12"),
+//    XMM13 = (30, "xmm13"),
+//    XMM14 = (31, "xmm14"),
+//    XMM15 = (32, "xmm15"),
+//
+//    ST0 = (33, "st0"),
+//    ST1 = (34, "st1"),
+//    ST2 = (35, "st2"),
+//    ST3 = (36, "st3"),
+//    ST4 = (37, "st4"),
+//    ST5 = (38, "st5"),
+//    ST6 = (39, "st6"),
+//    ST7 = (40, "st7"),
+//
+//    MM0 = (41, "mm0"),
+//    MM1 = (42, "mm1"),
+//    MM2 = (43, "mm2"),
+//    MM3 = (44, "mm3"),
+//    MM4 = (45, "mm4"),
+//    MM5 = (46, "mm5"),
+//    MM6 = (47, "mm6"),
+//    MM7 = (48, "mm7"),
+//
+//    RFLAGS = (49, "rFLAGS"),
+//    ES = (50, "es"),
+//    CS = (51, "cs"),
+//    SS = (52, "ss"),
+//    DS = (53, "ds"),
+//    FS = (54, "fs"),
+//    GS = (55, "gs"),
+//
+//    FS_BASE = (58, "fs.base"),
+//    GS_BASE = (59, "gs.base"),
+//
+//    TR = (62, "tr"),
+//    LDTR = (63, "ldtr"),
+//    MXCSR = (64, "mxcsr"),
+//    FCW = (65, "fcw"),
+//    FSW = (66, "fsw"),
+//
+//    XMM16 = (67, "xmm16"),
+//    XMM17 = (68, "xmm17"),
+//    XMM18 = (69, "xmm18"),
+//    XMM19 = (70, "xmm19"),
+//    XMM20 = (71, "xmm20"),
+//    XMM21 = (72, "xmm21"),
+//    XMM22 = (73, "xmm22"),
+//    XMM23 = (74, "xmm23"),
+//    XMM24 = (75, "xmm24"),
+//    XMM25 = (76, "xmm25"),
+//    XMM26 = (77, "xmm26"),
+//    XMM27 = (78, "xmm27"),
+//    XMM28 = (79, "xmm28"),
+//    XMM29 = (80, "xmm29"),
+//    XMM30 = (81, "xmm30"),
+//    XMM31 = (82, "xmm31"),
+//
+//    K0 = (118, "k0"),
+//    K1 = (119, "k1"),
+//    K2 = (120, "k2"),
+//    K3 = (121, "k3"),
+//    K4 = (122, "k4"),
+//    K5 = (123, "k5"),
+//    K6 = (124, "k6"),
+//    K7 = (125, "k7"),
diff --git a/src-self-hosted/ir.zig b/src-self-hosted/ir.zig
@@ -87,7 +87,6 @@ pub const Inst = struct {
                 .alloc,
                 .retvoid,
                 .unreach,
-                .arg,
                 .breakpoint,
                 .dbg_stmt,
                 => NoOp,
@@ -115,6 +114,7 @@ pub const Inst = struct {
                 .store,
                 => BinOp,
 
+                .arg => Arg,
                 .assembly => Assembly,
                 .block => Block,
                 .br => Br,
@@ -253,6 +253,20 @@ pub const Inst = struct {
         }
     };
 
+    pub const Arg = struct {
+        pub const base_tag = Tag.arg;
+
+        base: Inst,
+        name: [*:0]const u8,
+
+        pub fn operandCount(self: *const Arg) usize {
+            return 0;
+        }
+        pub fn getOperand(self: *const Arg, index: usize) ?*Inst {
+            return null;
+        }
+    };
+
     pub const Assembly = struct {
         pub const base_tag = Tag.assembly;