Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · be42f75 · be42f75
1 parent d4807ce
commit be42f75
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -186,7 +186,7 @@ architecture struct of controller is
          ResultSrc:      out STD_ULOGIC_VECTOR(1 downto 0);
          ALUSrc:         out STD_ULOGIC_VECTOR(1 downto 0);
          MemWrite:       out STD_ULOGIC;
-         Branch:          out STD_ULOGIC;
+         Branch:         out STD_ULOGIC;
          RegWrite, Jump: out STD_ULOGIC;
          ImmSrc:         out STD_ULOGIC_VECTOR(2 downto 0); -- 1 down to 0 before
          ALUOp:          out STD_ULOGIC_VECTOR(1 downto 0);
@@ -239,13 +239,13 @@ begin
       when "1100011" => case funct3 is           -- B-type
         when "000" => controls <= "001000000101000"; -- beq
         when "100" => controls <= "0010000--110010"; -- blt
-        when others => controls <= "-----------"; -- not valid
+        when others => controls <= "---------------"; -- not valid
         end case; 
       when "0010011" => controls <= "1000010000100-0"; -- I-type ALU
       when "1101111" => controls <= "1011000100001-0"; -- jal
       when "1100111" => controls <= "1000010100001-0"; -- jalr
       when "0010111" => controls <= "1100100000000-1"; -- U-Type (auipc)
-      when others    => controls <= "-----------"; -- not valid
+      when others    => controls <= "---------------"; -- not valid
     end case;
   end process;