Update riscvsingle.vhdl

AlexFW16 · Jun 2, 2023 · d4807ce · d4807ce
1 parent a792ede
commit d4807ce
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
@@ -204,8 +204,8 @@ architecture struct of controller is
   signal Branch: STD_ULOGIC;
   signal Jump_s : STD_ULOGIC;
 begin
-  md: maindec port map(op, funct3, ResultSrc, MemWrite, Branch,
-                       ALUSrc, RegWrite, Jump_s, ImmSrc, ALUOp);
+  md: maindec port map(op, funct3, ResultSrc, ALUSrc, MemWrite, Branch, 
+                      RegWrite, Jump_s, ImmSrc, ALUOp);
   ad: aludec port map(op(5), funct3, funct7b5, ALUOp, ALUControl);
 
   PCSrc <= (Branch and Zero) or Jump_s;