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Update riscvsingle.vhdl
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michael9186 committed Jun 2, 2023
1 parent 58b83c5 commit e5e8cd4
Showing 1 changed file with 1 addition and 2 deletions.
3 changes: 1 addition & 2 deletions project/template_2/riscvsingle.vhdl
Original file line number Diff line number Diff line change
Expand Up @@ -615,8 +615,7 @@ end;
architecture behave of shifter is -- shift a left by b (as int)
begin
--y <= a sll to_integer(unsigned(b));
shift_amount <= to_integer(unsigned(b(4 downto 0)));
y <= std_logic_vector(shift_left(signed(a), shift_amount));
y <= std_logic_vector(shift_left(signed(a), to_integer(unsigned(b(4 downto 0)))));
end;


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