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@HoneyGol-Microsystems

HoneyGol Microsystems

HoneyGol Microsystems

This organization hosts mainly VESP-related projects.

The VESP is a RISC-V microprocessor designed at FIT CTU in Prague as a student project.

Popular repositories Loading

  1. vesp-alpha vesp-alpha Public archive

    RISC-V based student processor for embedded applications.

    SystemVerilog 3

  2. riscv-tests riscv-tests Public

    Forked from riscv-software-src/riscv-tests

    C 1

  3. vesp-jtag vesp-jtag Public

    Forked from diegoherranz/steppenprobe

    Open Source Hardware JTAG/UART/GPIO interface board

    1

  4. jtag-example-basys3 jtag-example-basys3 Public

    Forked from freecores/jtag

    JTAG Test Access Port (TAP)

    Verilog

  5. wb-modules wb-modules Public

    Various Wishbone modules for VESP project.

    SystemVerilog

  6. wb2axip wb2axip Public

    Forked from ZipCPU/wb2axip

    Bus bridges and other odds and ends

    Verilog

Repositories

Showing 10 of 11 repositories
  • vesp-jtag Public Forked from diegoherranz/steppenprobe

    Open Source Hardware JTAG/UART/GPIO interface board

    HoneyGol-Microsystems/vesp-jtag’s past year of commit activity
    1 7 2 0 Updated Dec 3, 2024
  • jtag-example-basys3 Public Forked from freecores/jtag

    JTAG Test Access Port (TAP)

    HoneyGol-Microsystems/jtag-example-basys3’s past year of commit activity
    Verilog 0 GPL-3.0 13 0 0 Updated Dec 3, 2024
  • wbuart32 Public Forked from ZipCPU/wbuart32

    A simple, basic, formally verified UART controller

    HoneyGol-Microsystems/wbuart32’s past year of commit activity
    Verilog 0 GPL-3.0 48 0 0 Updated Nov 24, 2024
  • .github Public

    README repository.

    HoneyGol-Microsystems/.github’s past year of commit activity
    0 0 0 0 Updated Nov 16, 2024
  • wb-modules Public

    Various Wishbone modules for VESP project.

    HoneyGol-Microsystems/wb-modules’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Nov 16, 2024
  • sdspi Public Forked from ZipCPU/sdspi

    SD-Card controller, using either SPI, SDIO, or eMMC interfaces

    HoneyGol-Microsystems/sdspi’s past year of commit activity
    Verilog 0 38 0 0 Updated Nov 12, 2024
  • riscv-dbg Public Forked from pulp-platform/riscv-dbg

    RISC-V Debug Support for our PULP RISC-V Cores

    HoneyGol-Microsystems/riscv-dbg’s past year of commit activity
    SystemVerilog 0 78 0 0 Updated Nov 11, 2024
  • HoneyGol-Microsystems/riscv-tests’s past year of commit activity
    C 1 478 0 0 Updated Nov 8, 2024
  • wb2axip Public Forked from ZipCPU/wb2axip

    Bus bridges and other odds and ends

    HoneyGol-Microsystems/wb2axip’s past year of commit activity
    Verilog 0 101 0 0 Updated Nov 7, 2024
  • vesp-alpha Public archive

    RISC-V based student processor for embedded applications.

    HoneyGol-Microsystems/vesp-alpha’s past year of commit activity
    SystemVerilog 3 GPL-3.0 0 0 0 Updated Mar 13, 2024

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