This organization hosts mainly VESP-related projects.
The VESP is a RISC-V microprocessor designed at FIT CTU in Prague as a student project.
This organization hosts mainly VESP-related projects.
The VESP is a RISC-V microprocessor designed at FIT CTU in Prague as a student project.
RISC-V based student processor for embedded applications.
SystemVerilog 3
Forked from diegoherranz/steppenprobe
Open Source Hardware JTAG/UART/GPIO interface board
Forked from freecores/jtag
JTAG Test Access Port (TAP)
Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
This organization has no public members. You must be a member to see who’s a part of this organization.
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