Repositories list

• riscv-dbg

  Public
  RISC-V Debug Support for our PULP RISC-V Cores

  SystemVerilog

  •

  Other

  •78•0•0•0•Updated Jan 1, 2025Jan 1, 2025

• wb-modules

  Public
  Various Wishbone modules for VESP project.

  SystemVerilog

  •0•0•2•0•Updated Jan 1, 2025Jan 1, 2025

• pulp_common_cells

  Public
  Common SystemVerilog components of PULP platform.

  SystemVerilog

  •

  Other

  •148•0•0•0•Updated Dec 4, 2024Dec 4, 2024

• vesp-jtag

  Public
  Open Source Hardware JTAG/UART/GPIO interface board

  Other

  •6•1•2•0•Updated Dec 3, 2024Dec 3, 2024

• jtag-example-basys3

  Public
  JTAG Test Access Port (TAP)

  Verilog

  •

  GNU General Public License v3.0

  •13•0•0•0•Updated Dec 3, 2024Dec 3, 2024

• wbuart32

  Public
  A simple, basic, formally verified UART controller

  Verilog

  •

  GNU General Public License v3.0

  •48•0•0•0•Updated Nov 24, 2024Nov 24, 2024

• .github

  Public
  README repository.

  0•0•0•0•Updated Nov 16, 2024Nov 16, 2024

• sdspi

  Public
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces

  Verilog

  •38•0•0•0•Updated Nov 12, 2024Nov 12, 2024

• riscv-tests

  Public
  C

  •

  Other

  •471•1•0•0•Updated Nov 8, 2024Nov 8, 2024

• wb2axip

  Public
  Bus bridges and other odds and ends

  Verilog

  •101•0•0•0•Updated Nov 7, 2024Nov 7, 2024

• vesp-alpha

  Public archive
  RISC-V based student processor for embedded applications.

  SystemVerilog

  •

  GNU General Public License v3.0

  •0•3•0•0•Updated Mar 13, 2024Mar 13, 2024

• hdmi

  Public
  Send video/audio over HDMI on an FPGA

  SystemVerilog

  •

  Other

  •116•0•0•0•Updated Feb 3, 2024Feb 3, 2024