SystemVerilog Output

• SystemVerilog output structure
  • External registers and decoder hierarchy
  • Decoder interface types
    • Example rdl showing use of different decoder interfaces
    • Decoder interface IO descriptions
      • Parallel interface
      • Leaf interface
      • 8 bit serial interface
      • (8/16/32) bit ring interfaces
  • Secondary uP interfaces
  • Wrapper module/Interface encapsulation
  • Hardware side IO descriptions
  • Coverage info in SystemVerilog output
  • Using a gated clock for register logic
  • SystemVerilog output control parameters

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SystemVerilog output structure

Ordt generates a module named <name>_pio for each addrmap specified in RDL. Within <name>_pio two submodules are created: <name>_jrdl_decode and <name>_jrdl_logic which contain the address decode and register logic, respectively.

Nested addrmaps will result in cascaded <name>_pio modules. More information on generated RTL structure can be found here.

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Optional wrapper module

If use_interface, use_struct, use_new_interface, or use_new_struct properties are specified in rdl, a systemverilog wrapper module <name>_pio_iwrap will be created to provide interface encapsulated IO. The wrapper_info systemverilog output parameter will also cause the wrapper module to be created using the specified IO transforms. See here for additional information.

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Coverage info in SystemVerilog output

Ordt can embed coverpoints for field data using the rtl_coverage rdl property or for basic counter/interrupt input signals using the include_default_coverage control parameter.

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Using a gated logic clock

By default, ordt will provide a single clock input (clk) that drives all sequential logic in the generated RTL. If the use_gated_logic_clock control parameter is specified, a separate clock input (gclk) will be added to generated modules providing gated clock control of register logic. Generated decode modules will still use the ungated clock input (uclk) and will also provide a clock enable output that is activated upon module access by the uP and can be used to control an external clock gate. Note that control of gated clock logic in any address regions specified as external must be handled by the designer so that responses are generated correctly.

The gated_logic_access_delay access parameter can be used to delay start of transactions internal to the decoder by the specified number of clock cycles. Intent of this delay is to allow gated clocks from the external clock gate controlled by the decoder enable to stabilize before accessing register logic.