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Add secure paging support for plat-ti #1493

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merged 2 commits into from
Apr 28, 2017
+27 −4
Merged

Add secure paging support for plat-ti #1493

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a105bde
plat-ti: Remove duplicate SECRAM memory definition
glneo Apr 20, 2017
6e2a00b
plat-ti: Add secure paging support for DRA7xx/AM57xx
glneo Apr 20, 2017
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5 changes: 1 addition & 4 deletions core/arch/arm/plat-ti/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -54,16 +54,13 @@ static struct gic_data gic_data;
static struct serial8250_uart_data console_data __early_bss;
static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH];

register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE);
register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE);
register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
SERIAL8250_UART_REG_SIZE);

register_phys_mem(MEM_AREA_IO_SEC,
ROUNDDOWN(SECRAM_BASE, CORE_MMU_DEVICE_SIZE),
CORE_MMU_DEVICE_SIZE);

void main_init_gic(void)
{
vaddr_t gicc_base;
Expand Down
26 changes: 26 additions & 0 deletions core/arch/arm/plat-ti/platform_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,11 @@
#define TZDRAM_BASE 0xbdb00000
#define TZDRAM_SIZE 0x01c00000

#ifdef CFG_WITH_PAGER
#define TZSRAM_BASE 0x40300000
#define TZSRAM_SIZE (256 * 1024)
#endif /* CFG_WITH_PAGER */

#define CFG_TEE_CORE_NB_CORE 2

#define UART1_BASE 0x4806A000
Expand Down Expand Up @@ -111,6 +116,25 @@
/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64

#ifdef CFG_WITH_PAGER
/*
* Use TZSRAM for TEE, page out everything else to TZDRAM.
* +--------+----------+
* | DRAM | SHMEM |
* +--------+----------+
* | | TA_RAM |
* | TZDRAM +----------+
* | | PAGE_RAM |
* +--------+----------+
* | TZSRAM | TEE_RAM |
* +--------+----------+
*/
#define CFG_TEE_RAM_VA_SIZE (1 * 1024 * 1024)
#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE
#define CFG_TEE_RAM_START TZSRAM_BASE
#define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x1000)

#else /* CFG_WITH_PAGER */
/*
* Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
* everything is in TZDRAM.
Expand All @@ -127,6 +151,8 @@
#define CFG_TEE_RAM_START TZDRAM_BASE
#define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x100)

#endif /* CFG_WITH_PAGER */

#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
CORE_MMU_DEVICE_SIZE)
#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
Expand Down