Add secure paging support for plat-ti #1493
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jforissier
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Apr 24, 2017
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Please see my comment about the second commit.
For "plat-ti: Remove duplicate SECRAM memory definition": Acked-by: Jerome Forissier jerome.forissier@linaro.org`
core/arch/arm/plat-ti/main.c
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| @@ -50,6 +50,7 @@ | |||
| static struct gic_data gic_data; | |||
| static struct serial8250_uart_data console_data __early_bss; | |||
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| register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE); | |||
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Is this needed? And, if so, is this needed for this purpose ("Add secure paging support"), or should it be part of another patch? I'm wondering because TZDRAM_BASE is used already.
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This is needed, when building with CFG_WITH_PAGER the "tee-pageable.bin" is loaded to this area.
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Updated with Acked-by |
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After removing DEVICEx_TYPE/_PA_BASE/_SIZE support the definition for SECRAM was moved to main.c, but we had already made this move, remove the duplicate definition. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Add definitions for secure SRAM and DRAM space for builds with CFG_WITH_PAGER enabled. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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