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Enable write-implies-execute-never when applicable #1550

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merged 2 commits into from
May 29, 2017

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etienne-lms
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I'm not a big fan of this. Why add CFG_HWSUPP_MEM_PERM_WXN, and not just set CFG_CORE_RWDATA_NOEXEC only if you want it and your platform supports it?

@@ -189,6 +189,9 @@ UNWIND( .cantunwind)
orr r0, r0, #SCTLR_A
bic r0, r0, #SCTLR_C
bic r0, r0, #SCTLR_I
#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC)
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Better to test only CFG_CORE_RWDATA_NOEXEC here.
Optionally, add a dependency check in a core/arc/arm/arm.mk (but see my other comment, I feel the HWSUPP config is useless):

ifeq ($(CFG_CORE_RWDATA_NOEXEC))
ifneq ($(CFG_HWSUPP_MEM_PERM_WXN),y)
$(error ...)
endif
endif

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Some HW (C-A5, C-A9) do not support WXN and UWXN in SCTLR.
So we need this CFG_HWSUPP_MEM_PERM_WXN.
This is why the directive is not used in AARCH64, as all ARMv8-A do support SCTLR[WXN].

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I understand that. But we can simply assume that platforms that don't support CFG_CORE_RWDATA_NOEXEC simply don't enable it, no?

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No. At least for the few platforms lacking this hw hardening, op-tee core can still build a mmu that does rw-data-noexec. Weaker protection but at least optee legitimate mapping is clean.
The arm-tf does both: its mmu api never maps rwx memory and it sets STCRL[WXs], of course.

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Ah, now I get it. We really have two things to configure here. Sorry for the confusion.

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This commit ("core: factorize cpu support") is a good idea IMO.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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rebased

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So, for both patches:
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

HW may or may not support STCLR "WXN" configuration field.
CFG_HWSUPP_MEM_PERM_WXN reflects this state. AArch64 is assumed to
always support this field.

Enable the "WXN" (and UWXN) bits in STCLR upon configuration directive
CFG_CORE_RWDATA_NOEXEC.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Create core/arch/arm/cpu/<cpu-name>.mk to store CPU generic configurations
settings. Update supported platforms to rely on the generic CPU support.

Platform shall still specify whether they support or not the NEON
extension.

Cortex-A53 and Cortex-A57 are all ARMv8.0 compliant. For ARMv8 core,
we will use ARMv8-A architecture minor version configuration files.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Rebased, tag applied.

@jforissier jforissier merged commit 4389685 into OP-TEE:master May 29, 2017
@etienne-lms etienne-lms deleted the rxrorw3 branch May 30, 2017 11:19
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