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Enable write-implies-execute-never when applicable #1550

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merged 2 commits into from
May 29, 2017
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Enable write-implies-execute-never when applicable #1550

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58615a6
core: enable write-implies-execute-never when applicable
etienne-lms May 29, 2017
c285a78
core: factorize cpu support
etienne-lms May 23, 2017
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7 changes: 7 additions & 0 deletions core/arch/arm/cpu/cortex-a15.mk
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@@ -0,0 +1,7 @@
$(call force,CFG_ARM32_core,y)
$(call force,CFG_ARM64_core,n)
$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
arm32-platform-cpuarch := cortex-a15
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
7 changes: 7 additions & 0 deletions core/arch/arm/cpu/cortex-a7.mk
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@@ -0,0 +1,7 @@
$(call force,CFG_ARM32_core,y)
$(call force,CFG_ARM64_core,n)
$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
arm32-platform-cpuarch := cortex-a7
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
9 changes: 9 additions & 0 deletions core/arch/arm/cpu/cortex-a9.mk
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@@ -0,0 +1,9 @@
$(call force,CFG_ARM32_core,y)
$(call force,CFG_ARM64_core,n)
$(call force,CFG_WITH_LPAE,n)
$(call force,CFG_HWSUPP_MEM_PERM_WXN,n)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,n)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,n)
arm32-platform-cpuarch := cortex-a9
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
7 changes: 7 additions & 0 deletions core/arch/arm/cpu/cortex-armv8-0.mk
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@@ -0,0 +1,7 @@
$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
# cortex-a53 and cortex-a57 complies on arm32 architectures
arm32-platform-cpuarch := cortex-a53
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
platform-flavor-armv8 := 1
1 change: 1 addition & 0 deletions core/arch/arm/include/arm64.h
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Expand Up @@ -36,6 +36,7 @@
#define SCTLR_C BIT32(2)
#define SCTLR_SA BIT32(3)
#define SCTLR_I BIT32(12)
#define SCTLR_WXN BIT32(19)

#define TTBR_ASID_MASK 0xff
#define TTBR_ASID_SHIFT 48
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6 changes: 6 additions & 0 deletions core/arch/arm/kernel/generic_entry_a32.S
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Expand Up @@ -189,6 +189,9 @@ UNWIND( .cantunwind)
orr r0, r0, #SCTLR_A
bic r0, r0, #SCTLR_C
bic r0, r0, #SCTLR_I
#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC)
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Better to test only CFG_CORE_RWDATA_NOEXEC here.
Optionally, add a dependency check in a core/arc/arm/arm.mk (but see my other comment, I feel the HWSUPP config is useless):

ifeq ($(CFG_CORE_RWDATA_NOEXEC))
ifneq ($(CFG_HWSUPP_MEM_PERM_WXN),y)
$(error ...)
endif
endif

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Some HW (C-A5, C-A9) do not support WXN and UWXN in SCTLR.
So we need this CFG_HWSUPP_MEM_PERM_WXN.
This is why the directive is not used in AARCH64, as all ARMv8-A do support SCTLR[WXN].

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I understand that. But we can simply assume that platforms that don't support CFG_CORE_RWDATA_NOEXEC simply don't enable it, no?

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No. At least for the few platforms lacking this hw hardening, op-tee core can still build a mmu that does rw-data-noexec. Weaker protection but at least optee legitimate mapping is clean.
The arm-tf does both: its mmu api never maps rwx memory and it sets STCRL[WXs], of course.

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Ah, now I get it. We really have two things to configure here. Sorry for the confusion.

orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN)
#endif
write_sctlr r0
isb

Expand Down Expand Up @@ -446,6 +449,9 @@ UNWIND( .cantunwind)
mov r6, lr
read_sctlr r0
orr r0, r0, #SCTLR_A
#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC)
orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN)
#endif
write_sctlr r0

ldr r0, =_start
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6 changes: 6 additions & 0 deletions core/arch/arm/kernel/generic_entry_a64.S
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Expand Up @@ -73,6 +73,9 @@ FUNC _start , :

mrs x0, sctlr_el1
mov x1, #(SCTLR_I | SCTLR_A | SCTLR_SA)
#if defined(CFG_CORE_RWDATA_NOEXEC)
orr x1, x1, #SCTLR_WXN
#endif
orr x0, x0, x1
msr sctlr_el1, x0
isb
Expand Down Expand Up @@ -177,6 +180,9 @@ FUNC cpu_on_handler , :

mrs x0, sctlr_el1
mov x1, #(SCTLR_I | SCTLR_A | SCTLR_SA)
#if defined(CFG_CORE_RWDATA_NOEXEC)
orr x1, x1, #SCTLR_WXN
#endif
orr x0, x0, x1
msr sctlr_el1, x0
isb
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6 changes: 2 additions & 4 deletions core/arch/arm/plat-d02/conf.mk
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@@ -1,3 +1,5 @@
include core/arch/arm/cpu/cortex-armv8-0.mk

CFG_NUM_THREADS ?= 16
CFG_CRYPTO_WITH_CE ?= y
CFG_WITH_STACK_CANARIES ?= y
Expand All @@ -8,7 +10,6 @@ CFG_CORE_TZSRAM_EMUL_SIZE ?= 393216
CFG_CORE_HEAP_SIZE ?= 98304

$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_HI16XX_UART,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
Expand All @@ -18,9 +19,6 @@ $(call force,CFG_HI16XX_RNG,y)
endif

# 32-bit flags
arm32-platform-cpuarch := cortex-a57
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

ta-targets = ta_arm32
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6 changes: 2 additions & 4 deletions core/arch/arm/plat-hikey/conf.mk
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@@ -1,11 +1,9 @@
include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a53
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PL011,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
Expand Down
7 changes: 2 additions & 5 deletions core/arch/arm/plat-imx/conf.mk
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Expand Up @@ -23,11 +23,8 @@ endif


# Common i.MX6 config
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_ARM32_core,y)
$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_GIC,y)
$(call force,CFG_IMX_UART,y)
Expand All @@ -40,15 +37,15 @@ CFG_WITH_STACK_CANARIES ?= y

# i.MX6UL specific config
ifeq ($(CFG_MX6UL),y)
arm32-platform-cpuarch := cortex-a7
include core/arch/arm/cpu/cortex-a7.mk

$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
endif


# i.MX6 Solo/DualLite/Dual/Quad specific config
ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
arm32-platform-cpuarch := cortex-a9
include core/arch/arm/cpu/cortex-a9.mk

$(call force,CFG_PL310,y)
$(call force,CFG_PL310_LOCKED,y)
Expand Down
5 changes: 2 additions & 3 deletions core/arch/arm/plat-ls/conf.mk
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@@ -1,8 +1,7 @@
PLATFORM_FLAVOR ?= ls1021atwr

arm32-platform-cpuarch := cortex-a7
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
include core/arch/arm/cpu/cortex-a7.mk

core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_GENERIC_BOOT,y)
Expand Down
6 changes: 2 additions & 4 deletions core/arch/arm/plat-mediatek/conf.mk
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@@ -1,14 +1,12 @@
PLATFORM_FLAVOR ?= mt8173

include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a15
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mfpu=neon

$(call force,CFG_8250_UART,y)
$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
Expand Down
6 changes: 2 additions & 4 deletions core/arch/arm/plat-rcar/conf.mk
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@@ -1,13 +1,11 @@
PLATFORM_FLAVOR ?= h3

include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a57
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mfpu=neon

$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
Expand Down
6 changes: 2 additions & 4 deletions core/arch/arm/plat-rpi3/conf.mk
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@@ -1,12 +1,10 @@
include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a53
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_8250_UART,y)
$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
Expand Down
5 changes: 2 additions & 3 deletions core/arch/arm/plat-sprd/conf.mk
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@@ -1,9 +1,8 @@
PLATFORM_FLAVOR ?= sc9860

include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a15
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mfpu=neon

$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
Expand Down
5 changes: 2 additions & 3 deletions core/arch/arm/plat-stm/conf.mk
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@@ -1,8 +1,7 @@
PLATFORM_FLAVOR ?= b2260

arm32-platform-cpuarch := cortex-a9
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
include core/arch/arm/cpu/cortex-a9.mk

core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_ARM32_core,y)
Expand Down
5 changes: 2 additions & 3 deletions core/arch/arm/plat-sunxi/conf.mk
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@@ -1,6 +1,5 @@
arm32-platform-cpuarch := cortex-a15
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
include core/arch/arm/cpu/cortex-a15.mk

core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_ARM32_core,y)
Expand Down
7 changes: 2 additions & 5 deletions core/arch/arm/plat-ti/conf.mk
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Expand Up @@ -13,12 +13,11 @@ $(call force,CFG_NO_SMP,y)
$(call force,CFG_PL310,y)
$(call force,CFG_PL310_LOCKED,y)
$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
arm32-platform-cpuarch := cortex-a9
include core/arch/arm/cpu/cortex-a9.mk
else
CFG_OTP_SUPPORT ?= y
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
arm32-platform-cpuarch := cortex-a15
include core/arch/arm/cpu/cortex-a15.mk
endif
$(call force,CFG_SM_PLATFORM_HANDLER,y)
$(call force,CFG_GIC,y)
Expand All @@ -27,8 +26,6 @@ $(call force,CFG_DRA7_RNG,y)
endif

# 32-bit flags
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

ta-targets = ta_arm32
13 changes: 6 additions & 7 deletions core/arch/arm/plat-vexpress/conf.mk
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@@ -1,21 +1,21 @@
PLATFORM_FLAVOR ?= qemu_virt

# 32-bit flags
arm32-platform-cpuarch := cortex-a15
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

ifeq ($(PLATFORM_FLAVOR),qemu_virt)
include core/arch/arm/cpu/cortex-a15.mk
endif
ifeq ($(PLATFORM_FLAVOR),fvp)
platform-flavor-armv8 := 1
include core/arch/arm/cpu/cortex-armv8-0.mk
platform-debugger-arm := 1
endif
ifeq ($(PLATFORM_FLAVOR),juno)
platform-flavor-armv8 := 1
include core/arch/arm/cpu/cortex-armv8-0.mk
platform-debugger-arm := 1
endif
ifeq ($(PLATFORM_FLAVOR),qemu_armv8a)
platform-flavor-armv8 := 1
include core/arch/arm/cpu/cortex-armv8-0.mk
$(call force,CFG_DT,y)
endif

Expand All @@ -32,7 +32,6 @@ endif

$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_GIC,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PL011,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
Expand Down
4 changes: 1 addition & 3 deletions core/arch/arm/plat-zynq7k/conf.mk
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@@ -1,9 +1,7 @@
PLATFORM_FLAVOR ?= zc702

arm32-platform-cpuarch := cortex-a9
include core/arch/arm/cpu/cortex-a9.mk

arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
core_arm32-platform-aflags += -mfpu=neon

$(call force,CFG_ARM32_core,y)
Expand Down
6 changes: 2 additions & 4 deletions core/arch/arm/plat-zynqmp/conf.mk
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@@ -1,15 +1,13 @@
PLATFORM_FLAVOR ?= zcu102

include core/arch/arm/cpu/cortex-armv8-0.mk

# 32-bit flags
arm32-platform-cpuarch := cortex-a53
arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
arm32-platform-aflags += -mfpu=neon

$(call force,CFG_CDNS_UART,y)
$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_GIC,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
$(call force,CFG_PM_STUBS,y)
$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
Expand Down