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core: pager can use memory between SRAM start and core load address #1826

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merged 1 commit into from
Nov 15, 2017

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etienne-lms
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If core is loaded some 4kB pages above the start of the physical internal ram, some 4kB memory block will not be used by the pager.

This situation can occur if the beginning of the internal ram is used by a bootloader. Bootloader must load op-tee above its own used memory. Such bootloader memory is freely available to op-tee core (pager).

This change adds the physical memory between TEE RAM base address and the op-tee entry point address to the pager page pool. This change also default maps this area so that pager identifies physical pages as valid page addresses.

I found this issue while verifying support for various locations of a flat mapped coherent memory.

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With or without my comment addressed:
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

@@ -299,6 +297,10 @@ static void init_runtime(unsigned long pageable_part)
tee_pager_add_pages((vaddr_t)__pageable_start + init_size,
(pageable_size - init_size) / SMALL_PAGE_SIZE, true);

/* Pager can also use pages before unpaged memory if any */
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It could be worth commenting on when and why there may be pages before unpaged memory.

@jforissier
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@etienne-lms can you please rebase and address the conflicts with master?

@etienne-lms
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ok

@jforissier
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@etienne-lms I think you could have just applied Jens' R-b, no? Did you change something significant that he did not acknowledge?

@etienne-lms
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ok, i apply and squash.

If core is loaded some 4kB pages above the start of the physical
internal ram, some 4kB memory block will not be used by the pager.

This situation can occur if the beginning of the internal ram is
used by a bootloader. Bootloader must load op-tee above its own
used memory. Such bootloader memory is freely available to op-tee
core (pager).

This change adds the physical memory between TEE RAM base address
and the op-tee entry point address to the pager page pool. This
change also default maps this area so that pager identifies physical
pages as valid page addresses.

This changes fixes the plat-vexpress against CFG_TEE_RAM_START being
different from CFG_TEE_LOAD_ADDR.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
@jforissier
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Thanks!

@jforissier jforissier merged commit cc45d72 into OP-TEE:master Nov 15, 2017
@etienne-lms etienne-lms deleted the bottom branch February 9, 2018 13:01
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3 participants