0.4.0

0.4.0 update

• lib.Pipeline: a library for computation pipeline modeling as a dataflow is added.
• lib.FSM and lib.FSM: supporting prev() method to access the previous value of a reg.
• lib.Simulation: finish() method is added.
• to_verilog: number representation bugs are fixed.
• vtypes: IntX and IntZ are added. Object dump method str() is implemented for easy debugging. Type check capability is enhanced.

0.3.0

Veriloggen 0.3.0

• Better source code for both Python2.7 and Python3.4
• Some Verilog features are supported: initial, event, wait, system task, ...
• Some missing but basic operators are implemented.
• A feature for importing Verilog code is upgraded.
• New useful libraries: lib.parallel and lib.simulation
• Library update: lib.fsm
• A lot of examples are added and updated

0.2.0

Veriloggen 0.2.0 updates

• Two basic libraries (lib_fsm and lib_bundle)
• Almost basic syntaxes in Verilog HDL are supported
• type_check capability
• Supporting to import existing Verilog HDL source codes by using from_verilog
• Generate statement support
• Some new examples

0.1.3

Veriloggen 0.1.3

• Test code by using Pytest
• FSM library (lib.FSM) is updated
• Bit selection ([X:Y], [X]) operation is supported
• Bit concatenation (Cat) is supported
• Explicit function statement generation is supported

0.1.2

More Verilog-like description style is supported.

0.1.1

First public release.