1.7.0

Update

• Improvement of Fixed-Point (veriloggen.types.fixed, veriloggen.stream, veriloggen.thread)
• Added intermediate buffer operators: RingBuffer and Scratchpad (veriloggen.stream)
• Improvement of graph visualizer using pygraphviz (veriloggen.stream)
• Added reinterpret cast operator (veriloggen.stream)
• Added Split operator for SIMD-like processing (veriloggen.stream)
• Changed the default bit-width of AWUSER and ARUSER in AXI interfaces (veriloggen.types.axi, veriloggen.thread)

Test environment

Mac OSX 10.14.4

• Python 3.7.3
• Icarus Verilog 10.2
• Pyverilog 1.1.4

Ubuntu 18.04.2

• Python 3.6.7
• Icarus Verilog 10.1
• Pyverilog 1.1.4

1.6.0

Update

• Bug fix of Repeat operator (veriloggen.core)
• Bug fix of Shift-Right-Arithmetically operator (veriloggen.thread)
• Windows support (veriloggen.simulation)
• All of AXI interface signals are implemented in the AXI-based controllers. To create a complete AXI interface and IP-XACT, IPgen is no longer required. So IPgen is removed from the installation requirements.
• Updated the license description
• Added the contribution guideline

Test environment

Mac OSX 10.14.4

• Python 3.7.3
• Icarus Verilog 10.2
• Pyverilog 1.1.4

Ubuntu 18.04.2

• Python 3.6.7
• Icarus Verilog 10.1
• Pyverilog 1.1.4

1.5.4

Update

• Complement2, Abs, and Sign are implemented in veriloggen.core and stream.

Test environment

Mac OSX 10.14.2

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.3
• IPgen 1.0.1

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.3
• IPgen 1.0.1

1.5.3

Update

• RAM style attribute is supported.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.3
• IPgen 1.0.1

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.3
• IPgen 1.0.1

1.5.2

Update

• A bug fix of fixed point.
• __div__ and __truediv__ in Thread compiler are swapped.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.3
• IPgen 1.0.1

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.3
• IPgen 1.0.1

1.5.1

Update

• A bug fix for unused variable cares in Stream dump mode.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.3
• IPgen 1.0.1

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.3
• IPgen 1.0.1

1.5.0

Update

• No-check mode for Initial values of RAM is implemented.
• Fixed Point support is improved.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.3
• IPgen 1.0.1

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.3
• IPgen 1.0.1

1.4.4

Update

• Step number rule of Stream Dump mode is updated.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.4.3

Update

• Stream dump mode supports enable_dump() and disable_dump() methods from Thread.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.4.2

Update

• Bug fix of the dump format for RAM

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0