Add optimization_level=0 to transpiler for compiling dynamic circuits #2000
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doichanj
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…Qiskit#2000) ``id`` gate was removed by transpiler called from aer_compiler without optimization_level for dynamic circuits. This commits adds ``optimization_level=0`` to avoid removing id gates
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* add skip Python 3.12 for GPU build (#1965) * Fix basis gates of Aer backends (#1976) * move reset and switch_case ops to custom istr * Fix reset in AerStatevector * add test case * format * fix installing built Aer in some test cases * Applying global phase multiplication to initialize operation (#1980) * Applying global phase to initialize operation * fix format * remove recursive, add omp * Release 0.13.1 * Revert too many deprecations in Estimator (#1990) * Revert too much deprecation * fix typo * fix tests * Change priority of method selection of noise simulation (#1989) * Avoid selecting stabilizer method when noise model contains rotational gates * remove checking noise opsets, change priority selecting density_matrix * format * modify test cases use auto method result may change by this PR * modify one more test case * Remove use of opflow in Estimator (#1996) * Update misspelling apply_gate method doc (#1998) Co-authored-by: Jun Doi <doichan@jp.ibm.com> * Add optimization_level=0 to transpiler for compiling dynamic circuits (#2000) ``id`` gate was removed by transpiler called from aer_compiler without optimization_level for dynamic circuits. This commits adds ``optimization_level=0`` to avoid removing id gates * fix ry gate for stabilizer (#2001) Co-authored-by: Hiroshi Horii <hhorii@users.noreply.github.com> * Directly use psutil to get total system memory (#2002) Currently Aer is using Qiskit's local_hardware_info() function which to determine the total amount of system memory which is used to compute the largest statevector the system can build. However, this function wasn't really intended to be used outside of Qiskit and also Qiskit is looking to remove the memory reporting (see: Qiskit/qiskit#11254). This commit just pivots to using psutil directly which is what qiskit is doing internally. * test build fix (#2004) * Reverse ordering to read out error in sampling measure (#2003) * reverse ordering of read out error in sampling measure * fix batch check --------- Co-authored-by: Hiroshi Horii <hhorii@users.noreply.github.com> * Fix extended stabilizer thread safety in apply_ops_parallel (#1993) * Extended stabilizer simulator no longer shares RngEngine amongst states when ops are applied in parallel * Added release note * Fixed ugly cast --------- Co-authored-by: Jun Doi <doichan@jp.ibm.com> * add note (#1992) Co-authored-by: Jun Doi <doichan@jp.ibm.com> * Fix AerBackend issues caused by upgrading BackendV2 (#1995) * add description if no description is provided, build coupling map if it is provided * move import line * fix target for simulator backend * format * remove unused import * use translation plugin to rebuild gate sets for simulator * rename plugin * rebuild of gate sets is eanbled only for opt level 0 and 1 * fix custom pass manager * fix pass_manager function * added ccx in NAME_MAPPING * added missed gates in NAME_MAPPING * added release note * add check if opnodes is None * add check config * decrease return * check opt level * fix searching ops in control flow blocks * Update qiskit_aer/backends/plugin/aer_backend_plugin.py Co-authored-by: Matthew Treinish <mtreinish@kortar.org> * Update qiskit_aer/backends/plugin/aer_backend_plugin.py Co-authored-by: Matthew Treinish <mtreinish@kortar.org> * refer review comments * remove unused import --------- Co-authored-by: Matthew Treinish <mtreinish@kortar.org> * add prelude --------- Co-authored-by: Ikko Hamamura <ikkoham@users.noreply.github.com> Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com> Co-authored-by: jon <70080228+notcruz@users.noreply.github.com> Co-authored-by: Hiroshi Horii <hhorii@users.noreply.github.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org> Co-authored-by: eliotheinrich <38039898+eliotheinrich@users.noreply.github.com>
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Summary
This PR fixes issue #1997
Details and comments
id gate was removed by transpiler called from aer_compiler without optimization_level for dynamic circuits.
adding optimization_level=0 to avoid removing id gates