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Optimize1qGatesDecomposition doesn't account for ideal gates correctly #10568
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Following up on the discussion in #10592. |
This commit fixes an issue in Optimize1qGatesDecomposition where the pass would defer to synthesized gates if the output from synthesis was ideal even if the input gate was also ideal. This typically comes up in simulators where there are no error rates for any gates and everything is listed as ideal. This would cause the transpiler to translate gates unnecessarily which was unexpected. This commit fixes this by adding an additional check to the subsitution condition to ensure we're only substituting a gate if it's not in the target (when they're all ideal). Fixes Qiskit#10568
I hope you don't mind I was hitting this more frequently now that qiskit-aer is using |
…ion (#11351) * Don't substitute ideal gates in target with Optimize1qGatesDecomposition This commit fixes an issue in Optimize1qGatesDecomposition where the pass would defer to synthesized gates if the output from synthesis was ideal even if the input gate was also ideal. This typically comes up in simulators where there are no error rates for any gates and everything is listed as ideal. This would cause the transpiler to translate gates unnecessarily which was unexpected. This commit fixes this by adding an additional check to the subsitution condition to ensure we're only substituting a gate if it's not in the target (when they're all ideal). Fixes #10568 * Update releasenotes/notes/fix-optimize-1q-sim-407b88e45e6062b6.yaml Co-authored-by: Jake Lishman <jake@binhbar.com> * Update qiskit/transpiler/passes/optimization/optimize_1q_decomposition.py * Fix formatting --------- Co-authored-by: Jake Lishman <jake@binhbar.com>
…ion (#11351) * Don't substitute ideal gates in target with Optimize1qGatesDecomposition This commit fixes an issue in Optimize1qGatesDecomposition where the pass would defer to synthesized gates if the output from synthesis was ideal even if the input gate was also ideal. This typically comes up in simulators where there are no error rates for any gates and everything is listed as ideal. This would cause the transpiler to translate gates unnecessarily which was unexpected. This commit fixes this by adding an additional check to the subsitution condition to ensure we're only substituting a gate if it's not in the target (when they're all ideal). Fixes #10568 * Update releasenotes/notes/fix-optimize-1q-sim-407b88e45e6062b6.yaml Co-authored-by: Jake Lishman <jake@binhbar.com> * Update qiskit/transpiler/passes/optimization/optimize_1q_decomposition.py * Fix formatting --------- Co-authored-by: Jake Lishman <jake@binhbar.com> (cherry picked from commit f12db3b)
Not at all. Many thanks for the fix and sorry that I didn't manage to get to it sooner 🥲 |
…ion (#11351) (#11359) * Don't substitute ideal gates in target with Optimize1qGatesDecomposition This commit fixes an issue in Optimize1qGatesDecomposition where the pass would defer to synthesized gates if the output from synthesis was ideal even if the input gate was also ideal. This typically comes up in simulators where there are no error rates for any gates and everything is listed as ideal. This would cause the transpiler to translate gates unnecessarily which was unexpected. This commit fixes this by adding an additional check to the subsitution condition to ensure we're only substituting a gate if it's not in the target (when they're all ideal). Fixes #10568 * Update releasenotes/notes/fix-optimize-1q-sim-407b88e45e6062b6.yaml Co-authored-by: Jake Lishman <jake@binhbar.com> * Update qiskit/transpiler/passes/optimization/optimize_1q_decomposition.py * Fix formatting --------- Co-authored-by: Jake Lishman <jake@binhbar.com> (cherry picked from commit f12db3b) Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Environment
What is happening?
If a target has ideal gates with all error rates of 0 reported the output from the pass will translate from one gate to another unecessarily.
How can we reproduce the issue?
What should happen?
The output should remain as
h
because it's in the target and has the same error rate and gate count asUGate
. While both outputs are valid and the transpiler is doing it's job, in this situation it's a bit unexpected for the pass to translate the gate when the input was still valid and by the error heuristics no better or worse than the translated output.Any suggestions?
I think we probably need to add a condition to fallback to the input in the substitution checks if the output of all the synthesis routines are of equal weight.
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