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Don't substitute ideal gates in target with Optimize1qGatesDecomposition
This commit fixes an issue in Optimize1qGatesDecomposition where the pass would defer to synthesized gates if the output from synthesis was ideal even if the input gate was also ideal. This typically comes up in simulators where there are no error rates for any gates and everything is listed as ideal. This would cause the transpiler to translate gates unnecessarily which was unexpected. This commit fixes this by adding an additional check to the subsitution condition to ensure we're only substituting a gate if it's not in the target (when they're all ideal). Fixes Qiskit#10568
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releasenotes/notes/fix-optimize-1q-sim-407b88e45e6062b6.yaml
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--- | ||
fixes: | ||
- | | ||
Fixed an issue with the :class:`.Optimize1qGatesDecomposition` transpiler | ||
pass where it would potential resynthesize a single ideal (meaning the | ||
error rate is ``0.0``) gate which was present in the :class:`.Target`. This | ||
is now fixed so the pass :class:`.Optimize1qGatesDecomposition` will defer | ||
to the circuit's gate if the error rate (which includes number of gates) | ||
are the same. | ||
Fixed `#10568 <https://github.com/Qiskit/qiskit/issues/10568>`__ |
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