second attempt at combining clock generators

RIOT-OS · Aug 29, 2017 · 3f3e49d · 3f3e49d
1 parent 82d692b
commit 3f3e49d
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diff --git a/boards/arduino-mkr-common/include/periph_conf.h b/boards/arduino-mkr-common/include/periph_conf.h
@@ -31,26 +31,27 @@ extern "C" {
 #endif
 
 /**
- * @name    External oscillator and clock configuration
+ * @name External oscillator and clock configuration
  *
  * There are three choices for selection of CORECLOCK:
  *
- * - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
- * - usage of the internal 8MHz oscillator directly, divided by N if needed
- *
+ * CLOCK_USE_PLL: PLL fed by the internal 8Mhz oscillator
+ * CLOCK_USE_DFLL: DFLL fed by external 32.768 kHz oscillator
+ * CLOCK_USE_8MHZ: internal 8MHz oscillator
  *
  * The PLL option allows for the usage of a wider frequency range and a more
  * stable clock with less jitter. This is why this option is default.
  *
  * The target frequency is computed from the PLL multiplier and the PLL divisor.
  * Use the following formula to compute your values:
  *
- * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
+ * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / DIV
  *
  * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
  *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
  *
+ * The DFLL option can only be run at 48 MHz, but combined with an external
+ * oscillator it will provide the most clock stability.
  *
  * The internal Oscillator used directly can lead to a slightly better power
  * efficiency to the cost of a less stable clock. Use this option when you know
@@ -62,29 +63,8 @@ extern "C" {
  *
  * @{
  */
-#define CLOCK_USE_PLL               (1)
-#define CLOCK_USE_XOSC32_DFLL       (0)
-#define CLOCK_USE_8MHZ_DEFAULT      (0)
-
-#if CLOCK_USE_PLL
-    /* edit these values to adjust the PLL output frequency */
-#define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
-#define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
-    /* generate the actual used core clock frequency */
-#define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
-#elif CLOCK_USE_XOSC32_DFLL
-    /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
-#define CLOCK_CORECLOCK     (48000000UL)
-#define CLOCK_XOSC32K       (32768UL)
-#define GEN2_XOSC32         (1)
-#elif CLOCK_USE_8MHZ_DEFAULT
-    /* edit this value to your needs */
-#define CLOCK_DIV           (1U)
-    /* generate the actual core clock frequency */
-#define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
-#else
-#error Need to select a core clock
-#endif
+#define CLOCK_SRC                   (CLOCK_USE_PLL)
+#define CLOCK_CORECLOCK             (48000000U)
 /** @} */
 
 /**
@@ -240,7 +220,7 @@ static const spi_conf_t spi_config[] = {
 #define I2C_0_SCL           GPIO_PIN(PA, 9) /* SERCOM0-SCL, on-board pull-up */
 #define I2C_0_MUX           GPIO_MUX_C
 /** @} */
-    
+
 /**
  * @name RTC configuration
  * @{

diff --git a/boards/arduino-zero/include/periph_conf.h b/boards/arduino-zero/include/periph_conf.h
@@ -33,26 +33,27 @@ extern "C" {
 #endif
 
 /**
- * @name   External oscillator and clock configuration
+ * @name External oscillator and clock configuration
  *
  * There are three choices for selection of CORECLOCK:
  *
- * - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
- * - usage of the internal 8MHz oscillator directly, divided by N if needed
- *
+ * CLOCK_USE_PLL: PLL fed by the internal 8Mhz oscillator
+ * CLOCK_USE_DFLL: DFLL fed by external 32.768 kHz oscillator
+ * CLOCK_USE_8MHZ: internal 8MHz oscillator
  *
  * The PLL option allows for the usage of a wider frequency range and a more
  * stable clock with less jitter. This is why this option is default.
  *
  * The target frequency is computed from the PLL multiplier and the PLL divisor.
  * Use the following formula to compute your values:
  *
- * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
+ * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / DIV
  *
  * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
  *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
  *
+ * The DFLL option can only be run at 48 MHz, but combined with an external
+ * oscillator it will provide the most clock stability.
  *
  * The internal Oscillator used directly can lead to a slightly better power
  * efficiency to the cost of a less stable clock. Use this option when you know
@@ -64,29 +65,8 @@ extern "C" {
  *
  * @{
  */
-#define CLOCK_USE_PLL               (1)
-#define CLOCK_USE_XOSC32_DFLL       (0)
-#define CLOCK_USE_8MHZ_DEFAULT      (0)
-
-#if CLOCK_USE_PLL
-    /* edit these values to adjust the PLL output frequency */
-#define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
-#define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
-    /* generate the actual used core clock frequency */
-#define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
-#elif CLOCK_USE_XOSC32_DFLL
-    /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
-#define CLOCK_CORECLOCK     (48000000UL)
-#define CLOCK_XOSC32K       (32768UL)
-#define GEN2_XOSC32         (1)
-#elif CLOCK_USE_8MHZ_DEFAULT
-    /* edit this value to your needs */
-#define CLOCK_DIV           (1U)
-    /* generate the actual core clock frequency */
-#define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
-#else
-#error Need to select a core clock
-#endif
+#define CLOCK_SRC                   (CLOCK_USE_PLL)
+#define CLOCK_CORECLOCK             (48000000U)
 /** @} */
 
 /**
@@ -243,7 +223,7 @@ static const spi_conf_t spi_config[] = {
 #define RTT_ISR             isr_rtc
 #define RTT_MAX_VALUE       (0xffffffff)
 #define RTT_FREQUENCY       (32768U)    /* in Hz. For changes see `rtt.c` */
-#define XOSC32_RUNSTDBY     (1)         /* Keep RTT running in sleep states */
+#define RTT_RUNSTDBY        (1)         /* Keep RTT running in sleep states */
 /** @} */
 
 #ifdef __cplusplus

diff --git a/boards/samd21-xpro/include/periph_conf.h b/boards/samd21-xpro/include/periph_conf.h
@@ -32,26 +32,27 @@ extern "C" {
 #endif
 
 /**
- * @name   External oscillator and clock configuration
+ * @name    External oscillator and clock configuration
  *
  * There are three choices for selection of CORECLOCK:
  *
- * - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
- * - usage of the internal 8MHz oscillator directly, divided by N if needed
- *
+ * CLOCK_USE_PLL: PLL fed by the internal 8Mhz oscillator
+ * CLOCK_USE_DFLL: DFLL fed by external 32.768 kHz oscillator
+ * CLOCK_USE_8MHZ: internal 8MHz oscillator
  *
  * The PLL option allows for the usage of a wider frequency range and a more
  * stable clock with less jitter. This is why this option is default.
  *
  * The target frequency is computed from the PLL multiplier and the PLL divisor.
  * Use the following formula to compute your values:
  *
- * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
+ * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / DIV
  *
  * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
  *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
  *
+ * The DFLL option can only be run at 48 MHz, but combined with an external
+ * oscillator it will provide the most clock stability.
  *
  * The internal Oscillator used directly can lead to a slightly better power
  * efficiency to the cost of a less stable clock. Use this option when you know
@@ -63,29 +64,8 @@ extern "C" {
  *
  * @{
  */
-#define CLOCK_USE_PLL               (1)
-#define CLOCK_USE_XOSC32_DFLL       (0)
-#define CLOCK_USE_8MHZ_DEFAULT      (0)
-
-#if CLOCK_USE_PLL
-/* edit these values to adjust the PLL output frequency */
-#define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
-#define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
-/* generate the actual used core clock frequency */
-#define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
-#elif CLOCK_USE_XOSC32_DFLL
-/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
-#define CLOCK_CORECLOCK     (48000000UL)
-#define CLOCK_XOSC32K       (32768UL)
-#define GEN2_XOSC32         (1)
-#elif CLOCK_USE_8MHZ_DEFAULT
-/* edit this value to your needs */
-#define CLOCK_DIV           (1U)
-/* generate the actual core clock frequency */
-#define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
-#else
-#error Need to select a core clock
-#endif
+#define CLOCK_SRC                   (CLOCK_USE_8MHZ)
+#define CLOCK_CORECLOCK             (8000000U)
 /** @} */
 
 /**
@@ -274,7 +254,7 @@ static const spi_conf_t spi_config[] = {
 #define RTT_ISR             isr_rtc
 #define RTT_MAX_VALUE       (0xffffffff)
 #define RTT_FREQUENCY       (32768U)    /* in Hz. For changes see `rtt.c` */
-#define XOSC32_RUNSTDBY     (1)         /* Keep RTT running in sleep states */
+#define RTT_RUNSTDBY        (1)         /* Keep RTT running in sleep states */
 /** @} */
 
 /**

diff --git a/boards/samr21-xpro/include/periph_conf.h b/boards/samr21-xpro/include/periph_conf.h
@@ -32,26 +32,27 @@ extern "C" {
 #endif
 
 /**
- * @name   External oscillator and clock configuration
+ * @name    External oscillator and clock configuration
  *
  * There are three choices for selection of CORECLOCK:
  *
- * - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
- * - usage of the internal 8MHz oscillator directly, divided by N if needed
- *
+ * CLOCK_USE_PLL: PLL fed by the internal 8Mhz oscillator
+ * CLOCK_USE_DFLL: DFLL fed by external 32.768 kHz oscillator
+ * CLOCK_USE_8MHZ: internal 8MHz oscillator
  *
  * The PLL option allows for the usage of a wider frequency range and a more
  * stable clock with less jitter. This is why this option is default.
  *
  * The target frequency is computed from the PLL multiplier and the PLL divisor.
  * Use the following formula to compute your values:
  *
- * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
+ * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / DIV
  *
  * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
  *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
  *
+ * The DFLL option can only be run at 48 MHz, but combined with an external
+ * oscillator it will provide the most clock stability.
  *
  * The internal Oscillator used directly can lead to a slightly better power
  * efficiency to the cost of a less stable clock. Use this option when you know
@@ -63,29 +64,8 @@ extern "C" {
  *
  * @{
  */
-#define CLOCK_USE_PLL               (1)
-#define CLOCK_USE_XOSC32_DFLL       (0)
-#define CLOCK_USE_8MHZ_DEFAULT      (0)
-
-#if CLOCK_USE_PLL
-/* edit these values to adjust the PLL output frequency */
-#define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
-#define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
-/* generate the actual used core clock frequency */
-#define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
-#elif CLOCK_USE_XOSC32_DFLL
-/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
-#define CLOCK_CORECLOCK     (48000000UL)
-#define CLOCK_XOSC32K       (32768UL)
-#define GEN2_XOSC32         (1)
-#elif CLOCK_USE_8MHZ_DEFAULT
-/* edit this value to your needs */
-#define CLOCK_DIV           (1U)
-/* generate the actual core clock frequency */
-#define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
-#else
-#error Need to select a core clock
-#endif
+#define CLOCK_SRC                   (CLOCK_USE_PLL)
+#define CLOCK_CORECLOCK             (48000000U)
 /** @} */
 
 /**
@@ -247,7 +227,7 @@ static const spi_conf_t spi_config[] = {
 #define RTT_ISR             isr_rtc
 #define RTT_MAX_VALUE       (0xffffffff)
 #define RTT_FREQUENCY       (32768U)    /* in Hz. For changes see `rtt.c` */
-#define XOSC32_RUNSTDBY     (1)         /* Keep RTT running in sleep states */
+#define RTT_RUNSTDBY        (1)         /* Keep RTT running in sleep states */
 /** @} */
 
 /**

diff --git a/boards/sodaq-autonomo/include/periph_conf.h b/boards/sodaq-autonomo/include/periph_conf.h
@@ -29,26 +29,27 @@ extern "C" {
 #endif
 
 /**
- * @name   External oscillator and clock configuration
+ * @name    External oscillator and clock configuration
  *
  * There are three choices for selection of CORECLOCK:
  *
- * - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
- * - usage of the internal 8MHz oscillator directly, divided by N if needed
- *
+ * CLOCK_USE_PLL: PLL fed by the internal 8Mhz oscillator
+ * CLOCK_USE_DFLL: DFLL fed by external 32.768 kHz oscillator
+ * CLOCK_USE_8MHZ: internal 8MHz oscillator
  *
  * The PLL option allows for the usage of a wider frequency range and a more
  * stable clock with less jitter. This is why this option is default.
  *
  * The target frequency is computed from the PLL multiplier and the PLL divisor.
  * Use the following formula to compute your values:
  *
- * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
+ * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / DIV
  *
  * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
  *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
  *
+ * The DFLL option can only be run at 48 MHz, but combined with an external
+ * oscillator it will provide the most clock stability.
  *
  * The internal Oscillator used directly can lead to a slightly better power
  * efficiency to the cost of a less stable clock. Use this option when you know
@@ -60,29 +61,8 @@ extern "C" {
  *
  * @{
  */
-#define CLOCK_USE_PLL               (1)
-#define CLOCK_USE_XOSC32_DFLL       (0)
-#define CLOCK_USE_8MHZ_DEFAULT      (0)
-
-#if CLOCK_USE_PLL
-    /* edit these values to adjust the PLL output frequency */
-#define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
-#define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
-    /* generate the actual used core clock frequency */
-#define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
-#elif CLOCK_USE_XOSC32_DFLL
-    /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
-#define CLOCK_CORECLOCK     (48000000UL)
-#define CLOCK_XOSC32K       (32768UL)
-#define GEN2_XOSC32         (1)
-#elif CLOCK_USE_8MHZ_DEFAULT
-    /* edit this value to your needs */
-#define CLOCK_DIV           (1U)
-    /* generate the actual core clock frequency */
-#define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
-#else
-#error Need to select a core clock
-#endif
+#define CLOCK_SRC                   (CLOCK_USE_PLL)
+#define CLOCK_CORECLOCK             (48000000U)
 /** @} */
 
 /**
@@ -252,7 +232,7 @@ static const spi_conf_t spi_config[] = {
 #define RTT_ISR            isr_rtc
 #define RTT_MAX_VALUE      (0xffffffff)
 #define RTT_FREQUENCY      (32768U)    /* in Hz. For changes see `rtt.c` */
-#define XOSC32_RUNSTDBY    (1)         /* Keep RTT running in sleep states */
+#define RTT_RUNSTDBY       (1)         /* Keep RTT running in sleep states */
 /** @} */
 
 #ifdef __cplusplus