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19178: nanocoap_sock: store message ID in nanocoap_sock_t r=benpicco a=benpicco 19186: cpu/gd32v: add periph_rtc support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_rtc` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure `tests/periph_rtc` should work and should give the following output: ``` Help: Press s to start test, r to print it is ready START main(): This is RIOT! (Version: 2023.04-devel-144-gc17695-cpu/gd32v/periph_rtc) RIOT RTC low-level driver test This test will display 'Alarm!' every 2 seconds for 4 times Setting clock to 2020-02-28 23:59:57 Clock value is now 2020-02-28 23:59:57 Setting alarm to 2020-02-28 23:59:59 Alarm is set to 2020-02-28 23:59:59 Alarm cleared at 2020-02-28 23:59:57 No alarm at 2020-02-28 23:59:59 Setting alarm to 2020-02-29 00:00:01 Alarm! Alarm! Alarm! Alarm! ``` ### Issues/PRs references Co-authored-by: Benjamin Valentin <benjamin.valentin@bht-berlin.de> Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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/* | ||
* Copyright (C) 2019 Alexei Bezborodov | ||
* 2023 Gunar Schorcht | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @ingroup cpu_gd32v | ||
* @{ | ||
* @file | ||
* @brief Low-level RTC driver implementation for GD32VF103 | ||
* | ||
* This driver is a modified copy of the RTC driver for the STM32F1 family. | ||
* | ||
* @author Alexei Bezborodov <alexeibv+riotos@narod.ru> | ||
* @author Gunar Schorcht <gunar@schorcht.net> | ||
* @} | ||
*/ | ||
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#include <time.h> | ||
#include "cpu.h" | ||
#include "periph/rtc.h" | ||
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#define ENABLE_DEBUG 0 | ||
#include "debug.h" | ||
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#define EXTI_RTC_BIT (1UL << 17) | ||
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static struct { | ||
rtc_alarm_cb_t cb; /**< callback called from RTC interrupt */ | ||
void *arg; /**< argument passed to the callback */ | ||
} isr_ctx; | ||
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/* forward declaration of ISR */ | ||
static void isr_rtc_alarm(unsigned irqn); | ||
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static void _rtc_enter_config_mode(void) | ||
{ | ||
/* enable write access to backup domain registers */ | ||
PMU->CTL |= PMU_CTL_BKPWEN_Msk; | ||
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/* wait until the LWOFF bit is 1 (Last write operation finished). */ | ||
while ((RTC->CTL & RTC_CTL_LWOFF_Msk) == 0) { } | ||
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/* enter configuration mode. */ | ||
RTC->CTL |= RTC_CTL_CMF_Msk; | ||
} | ||
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static void _rtc_exit_config_mode(void) | ||
{ | ||
/* exit configuration mode. */ | ||
RTC->CTL &= ~RTC_CTL_CMF_Msk; | ||
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/* wait until the LWOFF bit is 1 (Last write operation finished). */ | ||
while ((RTC->CTL & RTC_CTL_LWOFF_Msk) == 0) { } | ||
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/* disable write access to backup domain registers */ | ||
PMU->CTL &= ~PMU_CTL_BKPWEN_Msk; | ||
} | ||
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static bool _is_rtc_enable(void) | ||
{ | ||
return ((RCU->BDCTL & RCU_BDCTL_RTCEN_Msk) == RCU_BDCTL_RTCEN_Msk); | ||
} | ||
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#define RCU_BDCTL_RTCSRC_CK_LXTAL 1 | ||
#define RCU_BDCTL_RTCSRC_CK_IRC40K 2 | ||
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static void _rtc_config(void) | ||
{ | ||
DEBUG("[RTC] config\n"); | ||
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/* enable APB1 clocks */ | ||
RCU->APB1EN |= RCU_APB1EN_PMUEN_Msk | RCU_APB1EN_BKPIEN_Msk; | ||
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/* enable write access to backup domain registers */ | ||
PMU->CTL |= PMU_CTL_BKPWEN_Msk; | ||
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/* resets the entire backup domain */ | ||
RCU->BDCTL |= RCU_BDCTL_BKPRST_Msk; | ||
/* reset not activated */ | ||
RCU->BDCTL &= ~RCU_BDCTL_BKPRST_Msk; | ||
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#if CONFIG_BOARD_HAS_LXTAL | ||
/* oscillator clock used as RTC clock */ | ||
RCU->BDCTL |= RCU_BDCTL_RTCSRC_CK_LXTAL << RCU_BDCTL_RTCSRC_Pos; | ||
RCU->BDCTL |= RCU_BDCTL_LXTALEN_Msk; | ||
while ((RCU->BDCTL & RCU_BDCTL_LXTALSTB_Msk) != RCU_BDCTL_LXTALSTB_Msk) { } | ||
#else | ||
RCU->BDCTL |= RCU_BDCTL_RTCSRC_CK_IRC40K << RCU_BDCTL_RTCSRC_Pos; | ||
#endif | ||
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/* enable RTC clock */ | ||
RCU->BDCTL |= RCU_BDCTL_RTCEN_Msk; | ||
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/* calibration clock from 0 to 0x7F */ | ||
BKP->OCTL |= 0; | ||
BKP->OCTL |= BKP_OCTL_ASOEN_Msk; | ||
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/* second interrupt is disabled. */ | ||
RTC->INTEN &= ~RTC_INTEN_SCIE_Msk; | ||
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_rtc_enter_config_mode(); | ||
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#if CONFIG_BOARD_HAS_LXTAL | ||
/* if the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in | ||
* this register to get a signal period of 1 second. */ | ||
RTC->PSCH = 0; | ||
RTC->PSCL = 0x7FFF; | ||
#else | ||
/* if the input clock frequency (fRTCCLK) is 40 kHz, write 39999 in | ||
* this register to get a signal period of 1 second. */ | ||
RTC->PSCH = 0; | ||
RTC->PSCL = 39999; | ||
#endif | ||
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_rtc_exit_config_mode(); | ||
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/* wait registers synchronize flag */ | ||
RTC->CTL &= (uint16_t)~RTC_CTL_RSYNF_Msk; | ||
while ((RTC->CTL & RTC_CTL_RSYNF_Msk) != RTC_CTL_RSYNF_Msk) { } | ||
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/* disable write access to backup domain registers */ | ||
PMU->CTL &= ~PMU_CTL_BKPWEN_Msk; | ||
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/* configure the EXTI channel, as RTC interrupts are routed through it. | ||
* Needs to be configured to trigger on rising edges. */ | ||
EXTI->FTEN &= ~(EXTI_RTC_BIT); | ||
EXTI->RTEN |= EXTI_RTC_BIT; | ||
EXTI->INTEN |= EXTI_RTC_BIT; | ||
EXTI->PD |= EXTI_RTC_BIT; | ||
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/* enable global RTC interrupt */ | ||
clic_set_handler(RTC_ALARM_IRQn, isr_rtc_alarm); | ||
clic_enable_interrupt(RTC_ALARM_IRQn, CPU_DEFAULT_IRQ_PRIO); | ||
} | ||
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static uint32_t _rtc_get_time(void) | ||
{ | ||
return (RTC->CNTH << 16) | RTC->CNTL; | ||
} | ||
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static void _rtc_set_time(uint32_t counter_val) | ||
{ | ||
_rtc_enter_config_mode(); | ||
RTC->CNTH = (counter_val & 0xffff0000) >> 16; | ||
RTC->CNTL = counter_val & 0x0000ffff; | ||
_rtc_exit_config_mode(); | ||
} | ||
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void rtc_init(void) | ||
{ | ||
/* save current time if RTC already works */ | ||
bool is_rtc_enable = _is_rtc_enable(); | ||
uint32_t cur_time = 0; | ||
if (is_rtc_enable) { | ||
cur_time = _rtc_get_time(); | ||
} | ||
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/* config RTC */ | ||
_rtc_config(); | ||
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/* restore current time after config */ | ||
if (is_rtc_enable) { | ||
_rtc_set_time(cur_time); | ||
} | ||
} | ||
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int rtc_set_time(struct tm *time) | ||
{ | ||
rtc_tm_normalize(time); | ||
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uint32_t timestamp = rtc_mktime(time); | ||
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_rtc_set_time(timestamp); | ||
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DEBUG("%s timestamp=%"PRIu32"\n", __func__, timestamp); | ||
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return 0; | ||
} | ||
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int rtc_get_time(struct tm *time) | ||
{ | ||
uint32_t timestamp = _rtc_get_time(); | ||
rtc_localtime(timestamp, time); | ||
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DEBUG("%s timestamp=%"PRIu32"\n", __func__, timestamp); | ||
return 0; | ||
} | ||
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static void _rtc_enable_alarm(void) | ||
{ | ||
/* clear alarm flag */ | ||
RTC->CTL &= ~RTC_CTL_ALRMIF_Msk; | ||
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_rtc_enter_config_mode(); | ||
RTC->INTEN |= (RTC_INTEN_ALRMIE_Msk); | ||
_rtc_exit_config_mode(); | ||
} | ||
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static void _rtc_disable_alarm(void) | ||
{ | ||
_rtc_enter_config_mode(); | ||
RTC->INTEN &= ~RTC_INTEN_ALRMIE_Msk; | ||
_rtc_exit_config_mode(); | ||
} | ||
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/* RTC->ALRMH and RTC->ALRML are writable only. Therefore the current alarm | ||
* time must be stored separately in a variable for _rtc_get_alarm_time. */ | ||
static uint32_t _rtc_alarm_time = 0; | ||
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static uint32_t _rtc_get_alarm_time(void) | ||
{ | ||
return _rtc_alarm_time; | ||
} | ||
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static void _rtc_set_alarm_time(uint32_t alarm_time) | ||
{ | ||
/* save the current alarm time */ | ||
_rtc_alarm_time = alarm_time; | ||
/* set RTC alarm registers */ | ||
_rtc_enter_config_mode(); | ||
RTC->ALRML = (alarm_time & 0x0000ffff); | ||
RTC->ALRMH = (alarm_time & 0xffff0000) >> 16; | ||
_rtc_exit_config_mode(); | ||
} | ||
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int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg) | ||
{ | ||
rtc_tm_normalize(time); | ||
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uint32_t timestamp = rtc_mktime(time); | ||
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/* disable existing alarm (if enabled) */ | ||
rtc_clear_alarm(); | ||
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/* save callback and argument */ | ||
isr_ctx.cb = cb; | ||
isr_ctx.arg = arg; | ||
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/* set wakeup time */ | ||
_rtc_set_alarm_time(timestamp); | ||
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/* enable Alarm */ | ||
_rtc_enable_alarm(); | ||
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DEBUG("%s timestamp=%"PRIu32"\n", __func__, timestamp); | ||
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return 0; | ||
} | ||
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int rtc_get_alarm(struct tm *time) | ||
{ | ||
uint32_t timestamp = _rtc_get_alarm_time(); | ||
rtc_localtime(timestamp, time); | ||
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DEBUG("%s timestamp=%"PRIu32"\n", __func__, timestamp); | ||
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return 0; | ||
} | ||
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void rtc_clear_alarm(void) | ||
{ | ||
_rtc_disable_alarm(); | ||
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isr_ctx.cb = NULL; | ||
isr_ctx.arg = NULL; | ||
} | ||
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void rtc_poweron(void) | ||
{ | ||
/* RTC is always on */ | ||
return; | ||
} | ||
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void rtc_poweroff(void) | ||
{ | ||
/* RTC is always on */ | ||
return; | ||
} | ||
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static void isr_rtc_alarm(unsigned irqn) | ||
{ | ||
(void)irqn; | ||
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if (RTC->CTL & RTC_CTL_ALRMIF_Msk) { | ||
if (isr_ctx.cb != NULL) { | ||
isr_ctx.cb(isr_ctx.arg); | ||
} | ||
RTC->CTL &= ~RTC_CTL_ALRMIF_Msk; | ||
} | ||
EXTI->PD |= EXTI_RTC_BIT; | ||
} |
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