cpu/gd32v: add periph_rtc support #19186
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19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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19185: cpu/gd32v: add periph_gpio_irq support r=gschorcht a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=gschorcht a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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Contribution description
This PR provides the
periph_rtcsupport and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.Testing procedure
tests/periph_rtcshould work and should give the following output:Issues/PRs references