cpu/gd32v: add periph_spi support

boards/common/gd32v/include/cfg_spi_default.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
+ *               2023 Gunar Schorcht <gunar@schorcht.net>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_common_gd32v
+ * @{
+ *
+ * @file
+ * @brief       Common peripheral configuration for GD32VF103 boards
+ *
+ * @author      Koen Zandberg <koen@bergzand.net>
+ * @author      Gunar Schorcht <gunar@schorcht.net>
+ */
+
+#ifndef CFG_SPI_DEFAULT_H
+#define CFG_SPI_DEFAULT_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name   SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SPI1,
+        .mosi_pin = GPIO_PIN(PORT_B, 15),
+        .miso_pin = GPIO_PIN(PORT_B, 14),
+        .sclk_pin = GPIO_PIN(PORT_B, 13),
+        .cs_pin   = GPIO_PIN(PORT_B, 12),
+        .rcumask  = RCU_APB1EN_SPI1EN_Msk,
+        .apbbus   = APB1,
+    },
+#ifndef MODULE_PERIPH_ADC
+    {
+        .dev      = SPI0,
+        .mosi_pin = GPIO_PIN(PORT_A, 7),
+        .miso_pin = GPIO_PIN(PORT_A, 6),
+        .sclk_pin = GPIO_PIN(PORT_A, 5),
+        .cs_pin   = GPIO_PIN(PORT_A, 4),
+        .rcumask  = RCU_APB2EN_SPI0EN_Msk,
+        .apbbus   = APB2,
+    },
+#endif
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CFG_SPI_DEFAULT_H */
+/** @} */

boards/seeedstudio-gd32/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SEEEDSTUDIO_GD32
     select BOARD_HAS_LXTAL
     select HAS_PERIPH_I2C
     select HAS_PERIPH_PWM
+    select HAS_PERIPH_SPI
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
     select HAVE_SAUL_GPIO

boards/seeedstudio-gd32/Makefile.features

@@ -3,6 +3,7 @@ CPU_MODEL = gd32vf103vbt6
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 

boards/seeedstudio-gd32/doc.txt

@@ -41,7 +41,7 @@ on-board components:
 | DAC         | 2 x 12-bit channel                     |   no      |
 | UART        | 2                                      |   yes     |
 | USART       | 3                                      |   yes     |
-| SPI         | 3                                      |   no      |
+| SPI         | 3                                      |   yes     |
 | I2C         | 2 x Fast Mode 400 kHz                  |   yes     |
 | I2S         | 2                                      |   no      |
 | CAN         | 2 x CAN 2.0B with up to 1 Mbps         |   no      |
@@ -64,9 +64,13 @@ MCU pins and their configuration in RIOT.
 
 | MCU Pin | MCU Peripheral | RIOT Peripheral  | Board Function | Remark                       |
 |:--------|:---------------|:-----------------|:---------------|:-----------------------------|
-| PA0     |                | BTN0             | KEY1           |                              |
+| PA0     | BOOT0          | BTN0             | KEY1           |                              |
 | PA9     | USART0 TX      | UART_DEV(0) TX   | UART TX        |                              |
 | PA10    | USART0 RX      | UART_DEV(0) RX   | UART RX        |                              |
+| PA4     | SPI1 CS        | SPI_DEV(1) CS    |                |                              |
+| PA5     | SPI1 SCLK      | SPI_DEV(1) SCLK  |                |                              |
+| PA6     | SPI1 MISO      | SPI_DEV(1) MISO  |                |                              |
+| PA7     | SPI1 MOSI      | SPI_DEV(1) MOSI  |                |                              |
 | PB0     |                | PWM_DEV(0) CH0   | LED1 green     |                              |
 | PB1     |                | PWM_DEV(0) CH1   | LED2 blue      |                              |
 | PB5     |                |                  | LED0 red       |                              |
@@ -76,9 +80,13 @@ MCU pins and their configuration in RIOT.
 | PB9     |                | PWM_DEV(1) CH1   |                | N/A if CAN is used           |
 | PB10    | I2C1 SCL       | I2C_DEV(1) SCL   |                |                              |
 | PB11    | I2C1 SDA       | I2C_DEV(1) SDA   |                |                              |
+| PB12    | SPI0 CS        | SPI_DEV(0) CS    |                |                              |
+| PB13    | SPI0 SCLK      | SPI_DEV(0) SCLK  |                |                              |
+| PB14    | SPI0 MISO      | SPI_DEV(0) MISO  |                |                              |
+| PB15    | SPI0 MOSI      | SPI_DEV(0) MOSI  |                |                              |
 | PC13    |                | BTN1             | KEY2           |                              |
 
-## Flash the board
+## Flashing the Device
 
 The board is flashed via a JTAG interface with OpenOCD (at least [release version 0.12.0]
 (https://github.com/openocd-org/openocd/tree/9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c)).

boards/seeedstudio-gd32/include/periph_conf.h

@@ -37,6 +37,7 @@
 #include "periph_common_conf.h"
 
 #include "cfg_i2c_default.h"
+#include "cfg_spi_default.h"
 #include "cfg_timer_default.h"
 #include "cfg_uart_default.h"
 

boards/sipeed-longan-nano/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SIPEED_LONGAN_NANO
     select BOARD_HAS_LXTAL
     select HAS_PERIPH_I2C
     select HAS_PERIPH_PWM
+    select HAS_PERIPH_SPI
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
     select HAVE_SAUL_GPIO

boards/sipeed-longan-nano/Makefile.features

@@ -3,6 +3,7 @@ CPU_MODEL = gd32vf103cbt6
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 

boards/sipeed-longan-nano/doc.txt

@@ -35,7 +35,7 @@ on-board components:
 | DAC         | 2 x 12-bit channel                     |   no      |
 | UART        | -                                      |   yes     |
 | USART       | 3                                      |   yes     |
-| SPI         | 3                                      |   no      |
+| SPI         | 3                                      |   yes     |
 | I2C         | 2 x Fast Mode 400 kHz                  |   yes     |
 | I2S         | 2                                      |   no      |
 | CAN         | 2 x CAN 2.0B with up to 1 Mbps         |   no      |
@@ -58,9 +58,13 @@ MCU pins and their configuration in RIOT.
 
 | MCU Pin | MCU Peripheral | RIOT Peripheral  | Board Function | Remark                       |
 |:--------|:---------------|:-----------------|:---------------|:-----------------------------|
-| PA0     | BOOT0          |                  | BTN0           |                              |
+| PA0     | BOOT0          | BTN0             | BOOT           |                              |
 | PA1     |                | PWM_DEV(0) CH0   | LED1 green     |                              |
 | PA2     |                | PWM_DEV(0) CH1   | LED2 blue      |                              |
+| PA4     | SPI1 CS        | SPI_DEV(1) CS    |                |                              |
+| PA5     | SPI1 SCLK      | SPI_DEV(1) SCLK  |                |                              |
+| PA6     | SPI1 MISO      | SPI_DEV(1) MISO  |                |                              |
+| PA7     | SPI1 MOSI      | SPI_DEV(1) MOSI  |                |                              |
 | PA9     | USART0 TX      | UART_DEV(0) TX   | UART TX        |                              |
 | PA10    | USART0 RX      | UART_DEV(0) RX   | UART RX        |                              |
 | PB6     | I2C0 SCL       | I2C_DEV(0) SCL   |                |                              |
@@ -69,6 +73,10 @@ MCU pins and their configuration in RIOT.
 | PB9     |                | PWM_DEV(1) CH1   |                | N/A if CAN is used           |
 | PB10    | I2C1 SCL       | I2C_DEV(1) SCL   |                |                              |
 | PB11    | I2C1 SDA       | I2C_DEV(1) SDA   |                |                              |
+| PB12    | SPI0 CS        | SPI_DEV(0) CS    |                |                              |
+| PB13    | SPI0 SCLK      | SPI_DEV(0) SCLK  |                |                              |
+| PB14    | SPI0 MISO      | SPI_DEV(0) MISO  |                |                              |
+| PB15    | SPI0 MOSI      | SPI_DEV(0) MOSI  |                |                              |
 | PC13    |                |                  | LED0 red       |                              |
 
 ## Flashing the Device

boards/sipeed-longan-nano/include/board.h

@@ -53,6 +53,27 @@ extern "C" {
 #define LED_BLUE_PIN        LED2_PIN    /**< LED2 is blue */
 /** @} */
 
+#if defined(MODULE_SDCARD_SPI)
+#define SDCARD_SPI_PARAM_SPI         SPI_DEV(0)
+#define SDCARD_SPI_PARAM_CS          GPIO_PIN(PORT_B, 12)
+#define SDCARD_SPI_PARAM_CLK         GPIO_PIN(PORT_B, 13)
+#define SDCARD_SPI_PARAM_MISO        GPIO_PIN(PORT_B, 14)
+#define SDCARD_SPI_PARAM_MOSI        GPIO_PIN(PORT_B, 15)
+#endif
+
+#if defined(MODULE_ST7735) && defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT)
+#define ST7735_PARAM_SPI          SPI_DEV(1)            /**< SPI device */
+#define ST7735_PARAM_SPI_CLK      SPI_CLK_5MHZ          /**< SPI clock frequency */
+#define ST7735_PARAM_SPI_MODE     SPI_MODE_0            /**< SPI mode */
+#define ST7735_PARAM_CS           GPIO_PIN(PORT_B, 2)   /**< Chip Select pin */
+#define ST7735_PARAM_DCX          GPIO_PIN(PORT_B, 0)   /**< DCX pin */
+#define ST7735_PARAM_RST          GPIO_PIN(PORT_B, 1)   /**< Reset pin */
+#define ST7735_PARAM_RGB          1                     /**< RGB mode enable */
+#define ST7735_PARAM_INVERTED     0                     /**< Inverted mode enable */
+#define ST7735_PARAM_NUM_LINES    160U                  /**< Number of lines */
+#define ST7735_PARAM_RGB_CHANNELS 80U                   /**< Number of columns */
+#endif
+
 #ifdef __cplusplus
 }
 #endif

boards/sipeed-longan-nano/include/periph_conf.h

@@ -37,6 +37,7 @@
 #include "periph_common_conf.h"
 
 #include "cfg_i2c_default.h"
+#include "cfg_spi_default.h"
 #include "cfg_timer_default.h"
 #include "cfg_uart_default.h"
 

cpu/gd32v/include/periph_cpu.h

@@ -205,22 +205,84 @@ typedef struct {
 #define UART_ISR_PRIO       (2)
 
 /**
- * @name    This CPU makes use of the following shared SPI functions
+ * @brief   Define a magic number that tells us to use hardware chip select
+ *
+ * We use a random value here, that does clearly differentiate from any possible
+ * GPIO_PIN(x) value.
+ */
+#define SPI_HWCS_MASK       (0xffffff00)
+
+/**
+ * @brief   Override the default SPI hardware chip select access macro
+ *
+ * Since the CPU does only support one single hardware chip select line, we can
+ * detect the usage of non-valid lines by comparing to SPI_HWCS_VALID.
+ */
+#define SPI_HWCS(x)         (SPI_HWCS_MASK | x)
+
+/**
+ * @brief   Define value for unused CS line
+ */
+#define SPI_CS_UNDEF        (GPIO_UNDEF)
+
+#ifndef DOXYGEN
+/**
+ * @brief   Overwrite the default spi_cs_t type definition
  * @{
  */
-#define PERIPH_SPI_NEEDS_TRANSFER_BYTE  1
-#define PERIPH_SPI_NEEDS_TRANSFER_REG   1
-#define PERIPH_SPI_NEEDS_TRANSFER_REGS  1
+#define HAVE_SPI_CS_T
+typedef uint32_t spi_cs_t;
+/** @} */
+#endif
+
+/**
+ * @brief   Use the shared SPI functions
+ * @{
+ */
+/** Use transfer byte function from periph common */
+#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
+/** Use transfer reg function from periph common */
+#define PERIPH_SPI_NEEDS_TRANSFER_REG
+/** Use transfer regs function from periph common */
+#define PERIPH_SPI_NEEDS_TRANSFER_REGS
+/** @} */
+
+/**
+ * @brief   Override SPI clock speed values
+ * @{
+ */
+#define HAVE_SPI_CLK_T
+enum {
+    SPI_CLK_100KHZ = KHZ(100), /**< drive the SPI bus with 100KHz */
+    SPI_CLK_400KHZ = KHZ(400), /**< drive the SPI bus with 400KHz */
+    SPI_CLK_1MHZ   = MHZ(1),   /**< drive the SPI bus with 1MHz */
+    SPI_CLK_5MHZ   = MHZ(5),   /**< drive the SPI bus with 5MHz */
+    SPI_CLK_10MHZ  = MHZ(10),  /**< drive the SPI bus with 10MHz */
+};
+
+/**
+ * @brief   SPI clock type
+ */
+typedef uint32_t spi_clk_t;
 /** @} */
 
 /**
  * @brief   Structure for SPI configuration data
  */
 typedef struct {
-    uint32_t addr;          /**< SPI control register address */
-    gpio_t mosi;            /**< MOSI pin */
-    gpio_t miso;            /**< MISO pin */
-    gpio_t sclk;            /**< SCLK pin */
+    SPI_Type *dev;          /**< SPI device base register address */
+    gpio_t mosi_pin;        /**< MOSI pin */
+    gpio_t miso_pin;        /**< MISO pin */
+    gpio_t sclk_pin;        /**< SCLK pin */
+    spi_cs_t cs_pin;        /**< HWCS pin, set to SPI_CS_UNDEF if not mapped */
+    uint32_t rcumask;       /**< bit in the RCC peripheral enable register */
+    uint8_t apbbus;         /**< APBx bus the device is connected to */
+#ifdef MODULE_PERIPH_DMA
+    dma_t tx_dma;           /**< Logical DMA stream used for TX */
+    uint8_t tx_dma_chan;    /**< DMA channel used for TX */
+    dma_t rx_dma;           /**< Logical DMA stream used for RX */
+    uint8_t rx_dma_chan;    /**< DMA channel used for RX */
+#endif
 } spi_conf_t;
 
 /**

cpu/gd32v/include/vendor/gd32vf103_periph.h

@@ -11555,9 +11555,9 @@ typedef struct {                                /*!< (@ 0x40002C00) WWDGT Struct
 //#define PMU_BASE                    0x40007000UL
 //#define RCU_BASE                    0x40021000UL
 //#define RTC_BASE                    0x40002800UL
-//#define SPI0_BASE                   0x40013000UL
-//#define SPI1_BASE                   0x40003800UL
-//#define SPI2_BASE                   0x40003C00UL
+#define SPI0_BASE                   0x40013000UL
+#define SPI1_BASE                   0x40003800UL
+#define SPI2_BASE                   0x40003C00UL
 #define TIMER0_BASE                 0x40012C00UL
 #define TIMER1_BASE                 0x40000000UL
 #define TIMER2_BASE                 0x40000400UL