cpu/stm32/eth: fix and improve ETH defines

cpu/stm32/include/periph/cpu_eth.h

@@ -96,7 +96,7 @@
  */
 #define RX_DESC_STAT_FL         (0x3FFF0000) /* bits 16-29 */
 #define RX_DESC_STAT_DE         (BIT14) /**< If set, a frame too large to fit buffers given by descriptors was received */
-#define RX_DESC_STAT_ES         (BIT14) /**< If set, an error occurred during RX */
+#define RX_DESC_STAT_ES         (BIT15) /**< If set, an error occurred during RX */
 #define RX_DESC_STAT_OWN        (BIT31) /**< If set, descriptor is owned by DMA, otherwise by CPU */
 /** @} */
 /**
@@ -117,10 +117,10 @@
  * @{
  */
 #define TX_DESC_STAT_UF         (BIT1)  /**< If set, an underflow occurred while sending */
 #define TX_DESC_STAT_EC         (BIT8)  /**< If set, TX was aborted due to excessive collisions (half-duplex only) */
 #define TX_DESC_STAT_NC         (BIT10) /**< If set, no carrier was detected (TX aborted) */
 #define TX_DESC_STAT_ES         (BIT15) /**< If set, one or more error occurred */
 #define TX_DESC_STAT_TTSS       (BIT17) /**< If set, the descriptor contains a valid PTP timestamp */
 /**
  * @brief   Indicates if TDES3 points to the next DMA descriptor (1), or to a second buffer (0)
  *
@@ -129,7 +129,7 @@
  * always set by the driver
  */
 #define TX_DESC_STAT_TCH        (BIT20)
 #define TX_DESC_STAT_TER        (BIT21) /**< If set, DMA will return to first descriptor in ring afterwards */
 /**
  * @brief   Checksum insertion control
  *
@@ -140,10 +140,14 @@
  * | `0b10` | Calculate and insert IPv4 checksum, insert pre-calculated payload checksum    |
  * | `0b11  | Calculated and insert both IPv4 and payload checksum                          |
  */
-#define TX_DESC_STAT_CIC        (BIT22 | BIT23)
+#define TX_DESC_STAT_CIC                    (BIT22 | BIT23)
+#define TX_DESC_STAT_CIC_NO_HW_CHECKSUM     (0)             /**< Do not compute checksums in hardware */
+#define TX_DESC_STAT_CIC_HW_CHECKSUM_IPV4   (BIT22)         /**< Compute the IPv4 header checksum in hardware */
+#define TX_DESC_STAT_CIC_HW_CHECKSUM_BOTH   (BIT22 | BIT32) /**< Compute the IPv4 header and payload checksum in hardware */
+
 #define TX_DESC_STAT_TTSE       (BIT25) /**< If set, an PTP timestamp is added to the descriptor after TX completed */
 #define TX_DESC_STAT_FS         (BIT28) /**< If set, buffer contains first segment of frame to transmit */
 #define TX_DESC_STAT_LS         (BIT29) /**< If set, buffer contains last segment of frame to transmit */
 #define TX_DESC_STAT_IC         (BIT30) /**< If set, trigger IRQ on completion */
 #define TX_DESC_STAT_OWN        (BIT31) /**< If set, descriptor is owned by DMA, otherwise by CPU */
 /** @} */
@@ -156,7 +160,7 @@
 void stm32_eth_common_init(void);
 #endif /* MODULE_PERIPH_ETH_COMMON */
 
 
 #ifdef __cplusplus
 }
 #endif