Haswell

Architecture specific notes for Intel® Haswell

Performance groups

Intel® Haswell Performance groups

Events

The input file for the events on Intel® Haswell can be found here.

Counters

• Core-local counters
  • Fixed-purpose counters
  • General-purpose counters
  • Thermal counter
• Socket-wide counters
  • Energy counters
  • Uncore global counters
  • Last level cache counters

Core-local counters

Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event.

Counters

Counter name	Event name
FIXC0	INSTR_RETIRED_ANY
FIXC1	CPU_CLK_UNHALTED_CORE
FIXC2	CPU_CLK_UNHALTED_REF

##### Available Options

Option	Argument	Description	Comment
anythread	N	Set bit 2+(index*4) in config register
kernel	N	Set bit (index*4) in config register

General-purpose counters

The Intel® Haswell microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

Counters

Counter name	Event name
PMC0	*
PMC1	*
PMC2	*
PMC3	*
PMC4	* (only available without HyperThreading)
PMC5	* (only available without HyperThreading)
PMC6	* (only available without HyperThreading)
PMC7	* (only available without HyperThreading)

Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
kernel	N	Set bit 17 in config register
anythread	N	Set bit 21 in config register
threshold	8 bit hex value	Set bits 24-31 in config register
invert	N	Set bit 23 in config register
in_transaction	N	Set bit 32 in config register	Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted	N	Set bit 33 in config register	Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available

Special handling for events

The Intel® Haswell microarchitecture provides measureing of offcore events in PMC counters. Therefore the stream of offcore events must be filtered using the OFFCORE_RESPONSE registers. The Intel® Haswell microarchitecture has two of those registers. LIKWID defines some events that perform the filtering according to the event name. Although there are many bitmasks possible, LIKWID natively provides only the ones with response type ANY. Own filtering can be applied with the OFFCORE_RESPONSE_0_OPTIONS and OFFCORE_RESPONSE_1_OPTIONS events. Only for those events two more counter options are available:

Option	Argument	Description	Comment
match0	16 bit hex value	Input value masked with 0x8077 and written to bits 0-15 in the OFFCORE_RESPONSE register	Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/HSW.
match0	22 bit hex value	Input value is written to bits 16-37 in the OFFCORE_RESPONSE register	Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/HSW.

The event MEM_TRANS_RETIRED_LOAD_LATENCY is not available because it needs programming of PEBS registers. PEBS is a kernel-level measurement facility. Although we can program it from user-space, the results are always 0.

Thermal counter

The Intel® Haswell microarchitecture provides one register for the current core temperature.

Counters

Counter name	Event name
TMP0	TEMP_CORE

Available Options

Option	Argument	Description	Comment
kernel	N	Clear exclude_kernel bit in struct perf_event_attr.

Socket-wide counters

Energy counters

The Intel® Haswell microarchitecture provides measurements of the current energy consumption through the RAPL interface.

Counters

Counter name	Event name
PWR0	PWR_PKG_ENERGY
PWR1	PWR_PP0_ENERGY
PWR2	PWR_PP1_ENERGY
PWR3	PWR_DRAM_ENERGY

Uncore global counters

The Intel® Haswell microarchitecture provides measurements for the global uncore management unit.

Counters

Counter name	Event name
UBOX0	*
UBOX1	*
UBOXFIX	UNCORE_CLOCK

##### Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
threshold	8 bit hex value	Set bits 24-28 in config register
invert	N	Set bit 23 in config register

Last level cache counters

The Intel® Haswell microarchitecture provides measurements for the last level cache segments.

Counters

Counter name	Event name
CBOX<0-3>C0	*
CBOX<0-3>C1	*

##### Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
threshold	8 bit hex value	Set bits 24-28 in config register
invert	N	Set bit 23 in config register