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Thomas Gruber edited this page Nov 1, 2023 · 1 revision

Architecture specific notes for Intel® SapphireRapids

Intel introduces with the IcelakeSP architecture a generic lookup and configuration mechanism for the Uncore units called "PMON Discovery mechanism" in the Uncore monitoring reference guide. The main idea is to provide the configuration of the performance monitoring units and their counters, called PMON blocks, at specific memory addresses to make it machine-readable. Although the Intel® Icelake SP introduced it, almost all addresses/offsets/bits were documented. With Intel® SapphireRapids, there are hardly any addresses/offsets/bits documented in the official documentation. Now, LIKWID has to perform the "PMON Discovery mechanism".

Performance groups

Intel® SappireRapids Performance groups

Events

The input file for the events on Intel® SappireRapids can be found here. The official event lists by Intel can be found here

Counters

Core-local counters

Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event.

Counters
Counter name Event name
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
FIXC3 TOPDOWN_SLOTS
Available Options
Option Argument Description Comment
anythread N Set bit 2+(index*4) in config register
kernel N Set bit (index*4) in config register

Performance metric counters

With the Intel® Icelake microarchitecture a new class of core-local counters was introduced, the so-called perf-metrics. The reflect the first level of the Top-down Microarchitecture Analysis tree.

Counters
Counter name Event name
TMA0 RETIRING
TMA1 BAD_SPECULATION
TMA2 FRONTEND_BOUND
TMA3 BACKEND_BOUND

The events return the fraction of slots used by the event.

General-purpose counters

The Intel® SapphireRapids microarchitecture provides 4 general-purpose counters consisting of a config and a counter register. If HyperThreading is disabled, each hardware thread provides 8 general-purpose counters.

Counters
Counter name Event name
PMC0 *
PMC1 *
PMC2 *
PMC3 *
PMC4 * (only available without HyperThreading)
PMC5 * (only available without HyperThreading)
PMC6 * (only available without HyperThreading)
PMC7 * (only available without HyperThreading)
Available Options
Option Argument Description Comment
edgedetect N Set bit 18 in config register
kernel N Set bit 17 in config register
anythread N Set bit 21 in config register The anythread option is deprecated! Please check the documentation how to use it on Icelake
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register
in_transaction N Set bit 32 in config register Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted N Set bit 33 in config register Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available

Thermal counter

The Intel® SapphireRapids microarchitecture provides one register for the current core temperature.

Counters
Counter name Event name
TMP0 TEMP_CORE

Core voltage counter

The Intel® SapphireRapids microarchitecture provides one register for the current core voltage.

Counters
Counter name Event name
VTG0 VOLTAGE_CORE

Socket-wide counters

Energy counters

The Intel® SapphireRapids microarchitecture provides measurements of the current energy consumption through the RAPL interface.

Counters
Counter name Event name
PWR0 PWR_PKG_ENERGY
PWR1 PWR_PP0_ENERGY
PWR2 PWR_PP1_ENERGY (*)
PWR3 PWR_DRAM_ENERGY
PWR4 PWR_PLATFORM_ENERGY (+)

(*) Commonly not supported (+) Often returns zeros

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