fix: chisel3 pr chipsalliance#2758

+ Replace MultiIOModule with Module;

src/main/scala/diplomacy/CloneModule.scala

@@ -7,7 +7,8 @@ package chisel3.shim
 
 import Chisel._
 import chisel3.experimental.BaseModule
-import chisel3.{RawModule, MultiIOModule}
+import chisel3.reflect.DataMirror
+import chisel3.{RawModule, Module}
 import chisel3.internal.Builder
 import chisel3.internal.firrtl.{Command, DefInstance}
 import scala.collection.immutable.ListMap
@@ -47,7 +48,7 @@ object CloneModule
     commands.update(victimIdx, standin)
     // Wire it up
     model match {
-      case _: MultiIOModule =>
+      case _: Module =>
         mod.io("clock") := Module.clock
         mod.io("reset") := Module.reset
       case _: RawModule => // Do nothing

src/main/scala/diplomacy/LazyModule.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.diplomacy
 
 import Chisel.{defaultCompileOptions => _, _}
 import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
-import chisel3.{MultiIOModule, RawModule, Reset, withClockAndReset}
+import chisel3.{Module, RawModule, Reset, withClockAndReset}
 import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord}
 import firrtl.passes.InlineAnnotation
 import freechips.rocketchip.config.Parameters
@@ -389,7 +389,7 @@ sealed trait LazyModuleImpLike extends RawModule {
   *
   * @param wrapper the [[LazyModule]] from which the `.module` call is being made.
   */
-class LazyModuleImp(val wrapper: LazyModule) extends MultiIOModule with LazyModuleImpLike {
+class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
   /** Instantiate hardware of this `Module`. */
   val (auto, dangles) = instantiate()
 }

src/main/scala/tilelink/Broadcast.scala

@@ -351,7 +351,7 @@ class ProbeFilterIO(val params: ProbeFilterParams) extends Bundle {
   val release = Flipped(Decoupled(new ProbeFilterRelease(params)))
 }
 
-abstract class ProbeFilter(val params: ProbeFilterParams) extends MultiIOModule {
+abstract class ProbeFilter(val params: ProbeFilterParams) extends Module {
   def useRegFields(bankIndex: Int): Seq[RegField.Map] = Nil
   def tieRegFields(bankIndex: Int): Unit = ()
   val io = IO(new ProbeFilterIO(params))

src/main/scala/unittest/UnitTest.scala

@@ -20,7 +20,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO {
   val io = new Bundle with UnitTestIO
 }
 
-trait UnitTestModule extends MultiIOModule with HasUnitTestIO {
+trait UnitTestModule extends Module with HasUnitTestIO {
   val io = IO(new Bundle with UnitTestIO)
   ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
 }