Skip to content

Releases: UCLA-VAST/splag

FPGA'22 Artifacts

05 Dec 05:47
@Blaok Blaok
fpga22
af451dc
Compare
Choose a tag to compare
FPGA'22 Artifacts Latest
Latest

This is the artifacts for the FPGA'22 paper, Accelerating SSSP for Power-Law Graphs. You will be able to reproduce the experiments presented in the paper using docker. This release contains the data files, pre-built bitstreams, and the instructions to build the docker images from source.

Prerequisites

To completely reproduce the experiments, the followings are required:

  • Docker on a x64 Linux server. To run the GPU experiments, the Nvidia container toolkit is required additionally.
  • Xilinx Alveo U280 FPGA with the xilinx_u280_xdma_201920_3 platform. This is the FPGA used in most experiments.
  • Xilnix Alveo U250 FPGA with the xilinx_u250_xdma_201830_2 platform. Without this FPGA, you won't be able to reproduce the comparison with ThunderGP and HitGraph.
  • Dual-socket Intel Xeon Gold 6244 CPU. Using a different CPU may lead to a very different comparison between SPLAG on U280 and CPU.
  • Nvidia A100 40 GB GPU. Without this GPU, you won't be able to reproduce the comparison between SPLAG on U280 and GPU.
  • A supported version of XRT.
  • A version of CUDA supported by the Nvidia docker images. nvidia-smi is needed to determine the CUDA version.
  • Vitis HLS 2020.2 and Vitis 2021.1, if you would like to build the FPGA bitstreams from source. Using different versions may lead to very different quality of results. Pre-built bitstreams are available and will be used by default.

Reproducing the Experiments

Obtaining the Source Code

The first step to reproduce the experiments is to clone the source repository. You don't need to download the data files manually; they will be pulled from the Internet as needed.

git clone https://github.com/UCLA-VAST/splag.git
cd splag/docker

Building the FPGA Bitstreams

By default, pre-built bitstreams will be downloaded and used. If you would like to build the bitstreams from source, you can do as follows. You should modify the two environment variables properly according to your local setup. The three bitstreams are for U280, VU5P, and U250, respectively. You may run them in parallel if you have sufficient memory. Generating a bitstream takes ~14 h.

# make sure you are in splag/docker
XILINX_HLS=/opt/tools/xilinx/Vitis_HLS/2020.2 XILINX_VIVADO=/opt/tools/xilinx/Vivado/2021.1 ./run.sh build-u280
mkdir -p data
cp build/u280/SSSP.xilinx_u280_xdma_201920_3.hw.xclbin data/SSSP.xilinx_u280_xdma_201920_3.hw.xclbin
# make sure you are in splag/docker
XILINX_HLS=/opt/tools/xilinx/Vitis_HLS/2020.2 XILINX_VIVADO=/opt/tools/xilinx/Vivado/2021.1 ./run.sh build-vu5p
mkdir -p data
cp build/vu5p/SSSP.xilinx_u250_xdma_201830_2.hw.xclbin data/SSSP.xilinx_u250_xdma_201830_2.vu5p.hw.xclbin
# make sure you are in splag/docker
XILINX_HLS=/opt/tools/xilinx/Vitis_HLS/2020.2 XILINX_VIVADO=/opt/tools/xilinx/Vivado/2021.1 ./run.sh build-u250
mkdir -p data
cp build/u250/SSSP.xilinx_u250_xdma_201830_2.hw.xclbin data/SSSP.xilinx_u250_xdma_201830_2.hw.xclbin

Running SPLAG on FPGA

To run the FPGA experiments, do as follows. It will take ~1 h.

# make sure you are in splag/docker
./run.sh fpga

Running the CPU Baseline

To run the CPU experiments, do as follows. Note that the output directory generated from the FPGA experiments are required. If you would like to run the CPU expriments on a different machine, make sure to copy the output directory.

# make sure you are in splag/docker
./run.sh cpu

Running the GPU Baseline

To run the GPU experiments, do as follows. Similar to the CPU experimetns, the output directory generated from the FPGA experiments are required. If you would like to run the GPU expriments on a different machine, make sure to copy the output directory.

# make sure you are in splag/docker
./run.sh gpu
Assets 52