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Welcome to the riscv-multi-core wiki!

The wiki will contain the documentation for the riscv-multi-core-lotr IP.

The 4 main components: GPC_4T, RC, LOTR, SW-Stack

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GPC_4T - Core + Memory

Core HAS: https://github.com/amichai-bd/riscv-multi-core-lotr/wiki/HAS-CORE-GPC_4T
Core MAS: https://github.com/amichai-bd/riscv-multi-core-lotr/wiki/MAS-CORE-GPC_4T
Writing in Systemverilog- in a "process agnostic" way - Compliant for Simulation, FPGA, ASIC. GPC - General Purpose Compute Unit

• 5 stage pipeline Core.
• 4 HW Threads.
• Supporting the RV32I/E ISA.
• continues local Memory for I_MEM, D_MEM and MMIO_CR

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RC - ring controller, Rout and Arbitrate requests

RC HAS: https://github.com/amichai-bd/riscv-multi-core-lotr/wiki/HAS-RING_CTRL-RC
RC MAS: https://github.com/amichai-bd/riscv-multi-core-lotr/wiki/MAS-RING_CTRL-RC

Writing in SystemVerilog- in a "process agnostic" way.

• Move data from cores to the Fabric (Ring)
• Move data from the Fabric (Ring) to the cores.
• Handle ordering, coherency, starvation, deadlocks.
  

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LOTR - Lord-Of-The-Ring - Fabric (integration model)

LOTR HAS: https://github.com/amichai-bd/riscv-multi-core-lotr/wiki/HAS-FABRIC-LOTR
The LOTR is the 'Fabric' - the "top-level" of the design.

1. Connects and pairs each 'core' to an 'RC' (ring controller) - LOTR_TILE.
2. Instantiates the LOTR_TILE (core&rc) in the fabric and connects all the TILE RC to each other in a ring architecture.

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Software Stack

Writing in C, Compiled using the riscv toolchain using the RV32I/E ISA (instruction set)

• Mainly to support the multithreaded core architecture, move data between cores.
• Handle Coherency, Deadlocks & Starvations.

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