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Fix printf in main of fpga_local_cmd #450

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Fix printf in main of fpga_local_cmd #450

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mbrobbel
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This fixes the following error:

fpga_local_cmd.c
fpga_local_cmd.c: In function ‘main’:
fpga_local_cmd.c:660:4: error: format not a string literal and no format arguments [-Werror=format-security]
    printf(long_help);
    ^

@rick-heig rick-heig mentioned this pull request Feb 26, 2019
Closed
mbrobbel added a commit to mbrobbel/fletcher that referenced this pull request Mar 29, 2019
@mbrobbel
Revert aws-fpga version bump. Blocked by
5b01cfc 
aws/aws-fpga#450
mbrobbel added a commit to abs-tudelft/fletcher that referenced this pull request Mar 29, 2019
@mbrobbel
Bump arrow from 0.11.1 to 0.12.0. Bump aws-fpga from 1.4.4 to 1.4.5. (#…
c726bf1 
…101)

* Update Arrow to 0.12 and update some other deps

* Use Bintray instead of Red-Data-Tools

* Fix link to keyring

* Update key for Arrow Bintray repository

* Make sure non-zero exit codes cause failure of job

* Fix typo

* Use unicode string literals

* Build echo for pyfletcher test

* Update aws-fpga to 1.4.6

* Bump arrow from 0.12.0 to 0.12.1. Bump aws_fpga from 1.4.6 to 1.4.7.

* Revert arrow bump from 0.12.0 to 0.12.1. Not available in bintray repo.

* Revert aws-fpga version bump. Blocked by 
aws/aws-fpga#450

* Attempt to fix pyfletcher test

* Remove comment from travis file
AWSaalluri added a commit that referenced this pull request Apr 11, 2019
@AWSaalluri
RELEASE V1.4.8
aad6da3 
* FPGA developer kit supports Xilinx SDx/Vivado 2018.3
* [Python bindings for AWS FPGA MGMT Tools](sdk/userspace/python_bindings/README.md)
* Fixed Issues
   * [Fixes printf in main of fpga_local_cmd](#450)
   * [Fixes SV dma read function to work with unprintable chars](#412)
   * [Fixes Segmentation Fault in cl_sde simulation test](https://forums.aws.amazon.com/thread.jspa?threadID=298946&tstart=0)
   * Fixes test issues in cl_dram_dma example when using the AXI memory model for faster simulations
* Deprecated Features
   * As announced in HDK 1.4.6 all EDMA driver code has been removed and deprecated from the developer kit.
AWSaalluri added a commit that referenced this pull request Apr 12, 2019
@AWSaalluri
RELEASE V1.4.8
9057c58 
* FPGA developer kit supports Xilinx SDx/Vivado 2018.3
* [Python bindings for AWS FPGA MGMT Tools](sdk/userspace/python_bindings/README.md)
* Fixed Issues
   * [Fixes printf in main of fpga_local_cmd](#450)
   * [Fixes SV dma read function to work with unprintable chars](#412)
   * [Fixes Segmentation Fault in cl_sde simulation test](https://forums.aws.amazon.com/thread.jspa?threadID=298946&tstart=0)
   * Fixes test issues in cl_dram_dma example when using the AXI memory model for faster simulations
* Deprecated Features
   * As announced in HDK 1.4.6 all EDMA driver code has been removed and deprecated from the developer kit.
AWSaalluri added a commit that referenced this pull request Apr 12, 2019
@AWSaalluri
RELEASE V1.4.8
0f67805 
* FPGA developer kit supports Xilinx SDx/Vivado 2018.3
* [Python bindings for AWS FPGA MGMT Tools](sdk/userspace/python_bindings/README.md)
* Fixed Issues
   * [Fixes printf in main of fpga_local_cmd](#450)
   * [Fixes SV dma read function to work with unprintable chars](#412)
   * [Fixes Segmentation Fault in cl_sde simulation test](https://forums.aws.amazon.com/thread.jspa?threadID=298946&tstart=0)
   * Fixes test issues in cl_dram_dma example when using the AXI memory model for faster simulations
* Deprecated Features
   * As announced in HDK 1.4.6 all EDMA driver code has been removed and deprecated from the developer kit.
@deeppat
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deeppat commented Apr 17, 2019

Hi @mbrobbel, we've released a fix in v1.4.8 so I'm closing this PR for now. Please feel free to re-open or reach out to us if it doesn't work for you!

Thanks,

Deep

@deeppat deeppat closed this Apr 17, 2019
kyyalama2 pushed a commit that referenced this pull request May 24, 2022
@AWSaalluri @kristopk
Xilinx sdaccel data retention (#450)
a2b2d0a 
* add support for dram data retention (#414)

* Added new github examples for ddr data retention (#426)

* Added new github examples for ddr data retention

* fixing link to runtime software test

* removing temporary & executable file from github

* new error codes for data retention (#445)

* Enable data retention. (#447)

* upgrading data retention branch to devkit  1.4.2

* porting backdoor DDR load & AXI_MEMORY_MODEL simulation features to data retention customer TB for future simulation support.

* updating default AFI to a data retention enabled 4-ddr calibration AFI

* updating dataretention branch to develop

* [2017.4 Data Retention] Backward compatibility (#454)

* Load without data retention if load failed

If failed for reasons FPGA_ERR_DRAM_DATA_RETENTION_NOT_POSSIBLE, FPGA_ERR_DRAM_DATA_RETENTION_FAILED, or FPGA_ERR_DRAM_DATA_RETENTION_SETUP_FAILED.

* Info message

Print an info message when load failed data retention.

* added data retention documentation (#453)

* added data retention documentation

* updated data retention docs

* Linking to data retention documents from top

* refining description of data retention feature

* adding asl license header for 2018

* fixing link for now. will add back after merging PR461

* Allow for spaces in a longer header comment

* Adding apache headers and updated asl 2018 header

* cl_dram_dma example cleanup (#461)

* added data retention documentation

* updated data retention docs

* created fpga_dma library

* customer example clean up for cl_dram_dma, plus data retention example

* cosim

* updated licence headers

* cosim-fix

* documentation updates for data retention (#462)

* doc updates

* doc updates

* doc updates

* doc updates

* doc updates

* adding sdaccel data retention example

* adding license header to Makefile

* fixing makefile switches

* fixing typo in license header
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@awshkulkar awshkulkar awshkulkar approved these changes

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4 participants
@mbrobbel @deeppat @awshkulkar @AWSaalluri