Xilinx XSim support
In addition to official support for ModelSim/QuestaSim and Verilator, SweRVolf can now also be simulated with Vivado XSim (versions 2020.1 and later)
SweRV EL2 support
SweRVolf was originally developed for SweRV EH1 but now also support SweRV EL2 for applicable targets.
Demo application
The Zephyr-based demo application now prints out detected clock frequency of the system as well as the CPU type (EL2/EH1)
Zephyr support
The Zephyr BSP for SweRVolf automatically detects the clock frequency at runtime and calculates timer intervals and UART baudrates accordingly during boot. This allows the same Zephyr binaries to be used on different SweRVolf implementations using different clock speeds.
GPIO remapping
The 32 upper GPIO have been moved on the memory map from 0x80001014 to 0x80001018 to allow space for a GPIO direction word adjacent to each GPIO bank. The upper 32 GPIO have not been used in any know SweRVolf implementation which is why this change is regarded as safe.
Basys3 support
In addition to the Digilent Nexys A7 board, the Digilent Basys3 board is now also supported providing a lower cost alternative for using SweRVolf. The smaller size of the FPGA on the Basys3 board only allows for SweRV EL2, not SweRV EH1
Documentation
An error in the boot switch arrangments was found and corrected for the Nexys A7 target. A link to a port of the Tock OS has also been added together with a link the the project page on LibreCores