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chipsalliance / chisel Public

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Back to pull request #3985

[svsim] Expose further verilator options for trace file name and simulation speed optimization #1499

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[svsim] Expose further verilator options for trace file name and simulation speed optimization

[svsim] Expose further verilator options for trace file name and simulation speed optimization #1499

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ci (ubuntu-22.04, 8, 2.13.12, 2.4) / Integration Tests

ci (ubuntu-22.04, 8, 2.13.12, 2.4) / Integration Tests

succeeded Apr 10, 2024 in 9m 30s

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